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1
JV70-CP Block Diagram
D
Project code: 91.4GC01.001 PCB P/N : 48.4GC01.011 REVISION : 09293--1
ATi
PCI EXPRESS GRAPHIC
PCB STACKUP
TOP VCC S
Clock Generator ICS9LRS3197AKLFT SLG8SP585VTR 3
DDRIII Slot 0 20 800/1066/1333 DDRIII Slot 1 21 800/1066/1333
DDRII Channel A
Arrandale Clarksfield
4,5,..,9,10
Intel CPU
X16
Madison Park
LVDS 2CH RGB CRT
VRAM sDDR3 1Gb*8
64...67
S GND BOTTOM
D
58...63
DDR II Channel B
DMIx4
FDIx8
Digital Display
SYSTEM DC/DC
TPS51123
CRT INPUTS
24 5V_S5 DCBATOUT 3D3V_S5 23 47
INTEL
Mini-Card WLAN 37
C
PCH RGB CRT
Switch Switch Switch
OUTPUTS
PCIE+USB 2.0
PCH
14 USB 2.0/1.1 ports ETHERNET (10/100/1000Mb) High Definition Audio
PCH LVDS 2CH
LCD WXGA+
SYSTEM DC/DC
TPS51117
INPUTS
DCBATOUT
PCH Digital Display
HDMI25
OUTPUTS
1D5V_S3 48
C
RJ45 CONN
Giga LAN
31
BCM57780
30
PCIE
6 SATA ports 8 PCIE ports ACPI 1.1 LPC I/F PCI/PCI BRIDGE USB 2.0
WEBCAM
SYSTEM DC/DC
23
TPS51117
INPUTS OUTPUTS
1D05V_S0 48
LINE IN MIC IN INT MIC
HD AUDIO CODEC ALC669X
32
BLUETOOTH 28 USB x 4 Card Reader AU6433
36 30
DCBATOUT
AZALIA
SYSTEM DC/DC
TPS51117
INPUTS OUTPUTS
1D05V_VTT 49
B
SD/MMC MS/MS Pro/xD 36
DCBATOUT
B
CPU DC/DC
OP AMP 2CH SPEAKER MAX 9789C 33
11,12,...,18,19
SPI
Flash ROM 4MB 41
ISL62883
INPUTS
DCBATOUT
OUTPUTS
VCC_CORE
45,46
LINE OUT
LPC Bus
LPC debug
40
MAXIM CHARGER
ISL88731A
INPUTS OUTPUTS BT+
51
MODEM RJ11 MDC CARD KBC NPCE781B
39 35
SPI
USB BD
09582-1 29
FP Base BD
09587-1 41
DCBATOUT
A
SATA HDD 26
SATA Thermal Sensor G787 38 Touch PAD 41 Int. KB39 Flash ROM 128KB 40
JV70-CP
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
SATA ODD
27
Block Diagram
Size A3 Date: Document Number Rev
JV70-CP
Thursday, October 08, 2009 Sheet
1
-1
1 of 68
5
4
3
2
PCH Strapping
Name
SPKR
A
B
Schematics Notes
Processor Strapping
Pin Name
CFG[4]
C
D
Default Value
1
E
Strap Description
Embedded DisplayPort Presence PCI-Express Static Lane Reversal PCI-Express Configuration Select Reserved Temporarily used for early Clarksfield samples.
Reboot option at power-up Default Mode: Internal weak Pull-down. No Reboot Mode with TCO Disabled: Connect to Vcc3_3 with 8.2-k - 10-k weak pull-up resistor. Weak internal pull-down. Do not pull high. Default Mode: Internal pull-up. Low (0) = Top Block Swap Mode (Connect to ground with 4.7-k pull-down resistor).
Configuration (Default value for each bit is 1 unless specified otherwise)
1: Disabled - No Physical Display Port attached to Embedded DisplayPort. 0: Enabled - An external Display Port device is connected to the Embedded Display Port. 1: Normal Operation. 0: Lane Numbers Reversed 15 -> 0, 14 -> 1, ... 1: Single PCI-Express Graphics 0: Bifurcation enabled Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor Note: Only temporary for early CFD samples (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common motherboard design (for AUB and CFD), the pull-down resistor should be used. Does not impact AUB functionality.
4
INIT3_3V# GNT3#/ GPIO55 INTVRMEN GNT0#, GNT1#
CFG[3] weak CFG[0]
1
4
1
High (1) = Integrated VRM is enabled Low (0) = Integrated VRM is disabled Default (SPI): Left both GNT0# and GNT1# floating. No pull up required. Boot from PCI: Connect GNT1# to ground with 1-k pull-down resistor. Leave GNT0# Floating. Boot from LPC: Connect both GNT0# and GNT1# to ground with 1-k pull-down resistor. Default - Internal pull-up. Low (0)= Configures DMI for ESI compatible operation (for servers only. Not for mobile/desktops). Default: Do not pull low. Disable ME in Manufacturing Mode: Connect to ground with 1-k pull-down resistor. Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Disable iTPM: Left floating, no pull-down required. Enable Danbury: Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Disable Danbury: Connect to ground with 4.7-k weak pull-down resistor. Weak internal pull-up. Do not pull low. Low (0): Flash Descriptor Security will be overridden. High (1) : Flash Descriptor Security will be in effect. Weak internal pull-down. Do not pull high. Weak internal pull-down. Do not pull high. Weak internal pull-down. Do not pull high. Weak internal pull-up. Do not pull low. Default = Do not connect (floating) High(1) = Enables the internal VccVRM to have a clean supply for analog rails. No need to use on-board filter circuit. Low (0) = Disables the VccVRM. Need to use on-board filter circuits for analog rails.
CFG[7]
0
GNT2#/ GPIO53 GPIO33
3
SPI_MOSI NV_ALE
3
NC_CLE HAD_DOCK_EN# /GPIO[33] HDA_SDO HDA_SYNC GPIO15 GPIO8 GPIO27
2
2
PCIE Routing
LANE1 LANE2 LAN MiniCard WLAN
Pair 0 1 2 3 4 5 6 7 8 9 10 11 12 13
USB
Device USB1 USB2 USB4 MINICARD1 WECAM NC NC NC NC USB3(HS) Finger Print Blue Tooth NC Cardreader
Title JV70-CP
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
Table of Content
Size A3 Date: Document Number Rev
JV70-CP
Thursday, October 08, 2009 Sheet 2 of 68
-1
A
B
C
D
E
3D3V_1D5V_CK505 1D5V_S0 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
2
1
C358
DY
4
2
3D3V_S0
R178 1 2 3D3V_1D5V_CK505 0R3J-0-U-GP
1
2
R174 0R3J-0-U-GP
1
C361
3D3V_S0
4
-1 0929
1 1 1 1 1 1 1
C355 SC10U6D3V3MX-GP C359 SC1U10V2ZY-GP C349 SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP C341 C351 SCD1U16V2ZY-2GP C340 SCD1U16V2ZY-2GP C339 SC1U10V2ZY-GP C356 SC10U6D3V3MX-GP
DY
DY
2
2
2
2
2
2
2
24
17
29
15
U24
VDDCPU_3_3
VDDSRC_3_3
VDDREF_3_3
VDDDOT96MHZ_3_3
VDDSRC_IO
VDD_27MHZ
VDDCPU_IO
18
1
5
-1 0923
27MHZ_NONSS 27MHZ_SS 6 7 16 25 30 28 27 31 32
VGA_XIN1_L R746 1 OSC_SPREAD_L R747 1 CPU_STOP# CLK_EN FSC
12 12 12 12
DREFCLK# DREFCLK CLKIN_DMI# CLKIN_DMI
1 1 1 1 1 1 1 1
R200 2 0R0402-PAD R204 2 0R0402-PAD R181 2 0R0402-PAD R182 2 0R0402-PAD R183 2 0R0402-PAD R184 2 0R0402-PAD R202 2 0R0402-PAD R207 2 0R0402-PAD
DREFCLK#_R DREFCLK_R CLKIN_DMI#_R CLKIN_DMI_R
ATI_ES DY
4 3 14 13
DOT96C_LPR DOT96T_LPR SRCC1_LPR SRCT1_LPR SATAC_LPR SATAT_LPR CPUC0_LPR CPUT0_LPR
2 0R2J-2-GP 2 0R2J-2-GP
2
1
1 R186 2 0R0603-PAD
3D3V_CK505
3D3V_CK505_IO SCD1U16V2ZY-2GP SCD1U16V2ZY-2GP
1 R180 2 0R0603-PAD
VGA_XIN1 59 OSC_SPREAD 59
3
12 CLK_PCIE_SATA# 12 CLK_PCIE_SATA 12 CLK_CPU_BCLK# 12 CLK_CPU_BCLK
CLK_PCIE_SATA#_R 11 CLK_PCIE_SATA_R 10 CLK_CPU_BCLK#_R 22 CLK_CPU_BCLK_R 23
CPU_STOP# CLKPWRGD/PD#_3_3 REF_3L/FSLC_3_3 X1 X2 GNDDOT96MHZ SDATA_3_3 SCLK_3_3 GNDSATA
3
R223 1
2 33R2J-2-GP 1
CLK_ICH14 12
GEN_XTAL_IN GEN_XTAL_OUT PCH_SMBDATA_1 PCH_SMBCLK_1
DY
1 R215 1 R211 2 2
PCH_SMBDATA 12,20,21 PCH_SMBCLK 12,20,21
C365 SC4D7P50V2CN-1GP SC4D7P50V2CN-1GP
19 20
GND27MHZ
CPUC1_LPR CPUT1_LPR GNDCPU GNDSRC GNDREF
0R0402-PAD 0R0402-PAD
2
8
33
26
21
71.93197.003 2ND = 71.08585.003
3D3V_S0
12
9
ICS9LRS3197AKLFT-GP-U
GND
4 3
RN25 SRN10KJ-5-GP
2 2
SC 0826
C360 SC12P50V2JN-3GP
1 2
FSC
1D05V_VTT GEN_XTAL_IN
0 133MHz (Default)
1 100MHz
CLK_EN
CPU_STOP#
1
2
SPEED
2
R219
82.30005.C51 2ND = 82.30005.901 X3 3RD = 82.30005.A51
XTAL-14D31818MHZ-21-GP
1
1
R218 10MR2J-L-GP
DY
2
GEN_XTAL_OUT
DY 2K2R2J-2-GP
2N7002-11-GP Q9 FSC
2
D
1
G S
2
1
2
GEN_XTAL_OUT_R 1 R213 2 0R0402-PAD
VR_CLKEN# 45
C363 SC12P50V2JN-3GP
-1 1005
2
R214 2K2R2J-2-GP
84.27002.W31 2ND = 84.27002.N31
CL=20pF±0.2pF
1
1
JV70-CP
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
Clock Generator
Size A3 Date:
A B C D
Document Number Thursday, October 08, 2009
Rev
JV70-CP
-1
3 of 68
E
Sheet
5
4
3
2
1
D
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3 DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3
CPU1A
1 OF 9
R137
DMI_RX0# DMI_RX1# DMI_RX2# DMI_RX3# DMI_RX0 DMI_RX1 DMI_RX2 DMI_RX3 DMI_TX0# DMI_TX1# DMI_TX2# DMI_TX3# DMI_TX0 DMI_TX1 DMI_TX2 DMI_TX3
AUBURNDALE
A24 C23 B22 A21 B24 D23 B23 A22 D24 G24 F23 H23 D25 F24 E23 G23
PEG_ICOMPI PEG_ICOMPO PEG_RCOMPO PEG_RBIAS PEG_RX0# PEG_RX1# PEG_RX2# PEG_RX3# PEG_RX4# PEG_RX5# PEG_RX6# PEG_RX7# PEG_RX8# PEG_RX9# PEG_RX10# PEG_RX11# PEG_RX12# PEG_RX13# PEG_RX14# PEG_RX15# PEG_RX0 PEG_RX1 PEG_RX2 PEG_RX3 PEG_RX4 PEG_RX5 PEG_RX6 PEG_RX7 PEG_RX8 PEG_RX9 PEG_RX10 PEG_RX11 PEG_RX12 PEG_RX13 PEG_RX14 PEG_RX15
B26 A26 B27 A25 K35 J34 J33 G35 G32 F34 F31 D35 E33 C33 D32 B32 C31 B28 B30 A31 J35 H34 H33 F35 G33 E34 F32 D34 F33 B33 D31 A32 C30 A28 B29 A30 L33 M35 M33 M30 L31 K32 M29 J31 K29 H30 H29 F29 E28 D29 D27 C26 L34 M34 M32 L30 M31 K31 M28 H31 K28 G30 G29 F28 E27 D28 C27 C25
PEG_IRCOMP_R EXP_RBIAS PEG_RXN15 PEG_RXN14 PEG_RXN13 PEG_RXN12 PEG_RXN11 PEG_RXN10 PEG_RXN9 PEG_RXN8 PEG_RXN7 PEG_RXN6 PEG_RXN5 PEG_RXN4 PEG_RXN3 PEG_RXN2 PEG_RXN1 PEG_RXN0 PEG_RXP15 PEG_RXP14 PEG_RXP13 PEG_RXP12 PEG_RXP11 PEG_RXP10 PEG_RXP9 PEG_RXP8 PEG_RXP7 PEG_RXP6 PEG_RXP5 PEG_RXP4 PEG_RXP3 PEG_RXP2 PEG_RXP1 PEG_RXP0 PEG_TXN15_L PEG_TXN14_L PEG_TXN13_L PEG_TXN12_L PEG_TXN11_L PEG_TXN10_L PEG_TXN9_L PEG_TXN8_L PEG_TXN7_L PEG_TXN6_L PEG_TXN5_L PEG_TXN4_L PEG_TXN3_L PEG_TXN2_L PEG_TXN1_L PEG_TXN0_L PEG_TXP15_L PEG_TXP14_L PEG_TXP13_L PEG_TXP12_L PEG_TXP11_L PEG_TXP10_L PEG_TXP9_L PEG_TXP8_L PEG_TXP7_L PEG_TXP6_L PEG_TXP5_L PEG_TXP4_L PEG_TXP3_L PEG_TXP2_L PEG_TXP1_L PEG_TXP0_L
1
R140
2 49D9R2F-GP 2 750R2F-GP
PEG_RXN[15..0] 58
D
1
DMI DMI
PEG_RXP[15..0] 58
C
13 13 13 13 13 13 13 13 13 13 13 13 13 13 13 13
FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7
E22 D21 D19 D18 G21 E19 F21 G18 D22 C21 D20 C18 G22 E20 F20 G19 F17 E17 C17 F18 D17
FDI_TX0# FDI_TX1# FDI_TX2# FDI_TX3# FDI_TX4# FDI_TX5# FDI_TX6# FDI_TX7# FDI_TX0 FDI_TX1 FDI_TX2 FDI_TX3 FDI_TX4 FDI_TX5 FDI_TX6 FDI_TX7 FDI_FSYNC0 FDI_FSYNC1 FDI_INT FDI_LSYNC0 FDI_LSYNC1
C
Intel(R) FDI
PCI EXPRESS -- GRAPHICS
13 FDI_FSYNC0 13 FDI_FSYNC1 13 FDI_INT 13 FDI_LSYNC0 13 FDI_LSYNC1
PEG_TX0# PEG_TX1# PEG_TX2# PEG_TX3# PEG_TX4# PEG_TX5# PEG_TX6# PEG_TX7# PEG_TX8# PEG_TX9# PEG_TX10# PEG_TX11# PEG_TX12# PEG_TX13# PEG_TX14# PEG_TX15# PEG_TX0 PEG_TX1 PEG_TX2 PEG_TX3 PEG_TX4 PEG_TX5 PEG_TX6 PEG_TX7 PEG_TX8 PEG_TX9 PEG_TX10 PEG_TX11 PEG_TX12 PEG_TX13 PEG_TX14 PEG_TX15
1
DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS DIS
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2
C160 C162 C164 C166 C168 C173 C174 C179 C186 C188 C195 C202 C214 C225 C229 C235 C161 C163 C165 C167 C169 C177 C180 C184 C190 C191 C197 C208 C222 C230 C233 C239
SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP SCD1U10V2KX-5GP
PEG_TXN15 PEG_TXN14 PEG_TXN13 PEG_TXN12 PEG_TXN11 PEG_TXN10 PEG_TXN9 PEG_TXN8 PEG_TXN7 PEG_TXN6 PEG_TXN5 PEG_TXN4 PEG_TXN3 PEG_TXN2 PEG_TXN1 PEG_TXN0 PEG_TXP15 PEG_TXP14 PEG_TXP13 PEG_TXP12 PEG_TXP11 PEG_TXP10 PEG_TXP9 PEG_TXP8 PEG_TXP7 PEG_TXP6 PEG_TXP5 PEG_TXP4 PEG_TXP3 PEG_TXP2 PEG_TXP1 PEG_TXP0
PEG_TXN[15..0] 58
B
RN26
DIS-ONLY
1 2 3 4 8 7 6 5
FDI_FSYNC1 FDI_LSYNC1 FDI_LSYNC0 FDI_FSYNC0
R541 1KR2J-1-GP
PEG_TXP[15..0] 58
B
SRN1KJ-4-GP
DIS-ONLY
For Graphics Disable , Pull-down to GND via 1-k ± 5% resistor
AUBURUNF,CLARKU1NF
2
62.10040.611 2ND = 62.10055.321
A
JV70-CP
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (1/7)
Size A3 Date: Document Number Rev
JV70-CP
Thursday, October 08, 2009 Sheet 4 of 68
-1
5
1D05V_VTT
4
CPU1B
3
2 OF 9
2
1
1
R496
2
20R2F-GP
H_COMP3 H_COMP2 20R2F-GP H_COMP1 49D9R2F-GP H_COMP0 49D9R2F-GP SKTOCC#_R H_CATERR#
AT23 AT24 G16 AT26 AH24 AK14
COMP3 COMP2 COMP1 COMP0 SKTOCC# CATERR#
1
R131
2
68R2-GP
PROCHOT# R154 R482
1 1
2 2
TP47
CLOCKS
R162
49D9R2F-GP
R486
AUBURNDALE
1
2
H_CATERR#
1
2
BCLK BCLK# BCLK_ITP BCLK_ITP# PEG_CLK PEG_CLK# DPLL_REF_SSCLK DPLL_REF_SSCLK#
A16 B16 AR30 AT30 E16 D16 A18 A17
BCLK_CPU_P BCLK_CPU_N
BCLK_CPU_P 16 BCLK_CPU_N 16
MISC MISC
D
PEG_CLK_R PEG_CLK#_R DPLL_REF_SSCLK DPLL_REF_SSCLK#
TPAD14-GP
1
PEG_CLK_R 12 PEG_CLK#_R 12 DPLL_REF_SSCLK 12 DPLL_REF_SSCLK# 12 SM_RCOMP_0 1 R190 SM_RCOMP_1 1 R188 SM_RCOMP_2 1 R189
2
100R2F-L1-GP-U
D
24D9R2F-L-GP
2 2
130R2F-1-GP
THERMAL THERMAL
SB 0814
SM_DRAMRST# SM_RCOMP0 SM_RCOMP1 SM_RCOMP2 PM_EXT_TS0# PM_EXT_TS1# F6 AL1 AM1 AN1 AN15 AP15
SM_DRAMRST# 16 SM_RCOMP_0 SM_RCOMP_1 SM_RCOMP_2 1D05V_VTT RN21 SRN10KJ-5-GP 1 4 2 3
16 H_PECI
AT15
PECI
45 H_PROCHOT#
R134 1
DY
2 0R2J-2-GP
PROCHOT#
AN26
PROCHOT#
PM_EXTTS#0_R 20 PM_EXTTS#1_R 21
16,43 PM_THRMTRIP-A#
AK15
THERMTRIP#
DDR3 MISC
PRDY# PREQ# TCK TMS TRST# TDI TDO TDI_M TDO_M DBR# BPM0# BPM1# BPM2# BPM3# BPM4# BPM5# BPM6# BPM7#
AT28 AP27 AN28 AP28 AT27 AT29 AR27 AR29 AP29 AN25 AJ22 AK22 AK24 AJ24 AJ25 AH22 AK23 AH23
XDP_PRDY# XDP_PREQ# XDP_TCLK XDP_TMS XDP_TRST# XDP_TDI XDP_TDO XDP_TDI_M XDP_TDO_M
1
TP43 TPAD14-GP DPLL_REF_SSCLK DPLL_REF_SSCLK# R744 2 0R0402-PAD R745 2 0R0402-PAD
TPAD14-GP
TP44
1
H_CPURST#
AP26 AL15
RESET_OBS# PM_SYNC VCCPWRGOOD_1 VCCPWRGOOD_0 SM_DRAMPWROK VTTPWRGOOD TAPPWRGOOD RSTIN#
1 1
PWR MANAGEMENT PWR MANAGEMENT
13 H_PM_SYNC 16,43,56 H_PW RGD
C
1 R146 2 0R0402-PAD 1 R144 2 0R0402-PAD
VCCPW RGOOD_1 VCCPW RGOOD_0 DRAMPW ROK H_VTTPW RGD
AN14 AN27 AK13 AM15 AM26 AL14
JTAG & BPM
XDP_DBRESET#
If supports integrated graphics but without eDP, these pins can also be connected to GND directly.
C
13 PM_DRAM_PW RGD 49 H_VTTPW RGD
1 R163 2 0R0402-PAD
TPAD14-GP R158 1
TP45
1 2
H_PW RGD_XDP PLT_RST#_R
15,30,36,37,39,40,56,58
PLT_RST#
3D3V_S0
1K5R2F-2-GP
1
R155 750R2F-GP
AUBURUNF,CLARKU1NF
XDP_DBRESET#
62.10040.611 2ND = 62.10055.321
1 R136
2 1KR2J-1-GP
R859 PM_DRAM_PW RGD 1
2
PM_DRAM_PW RGD_1
B
1D5V_S3
1K5R2F-2-GP
2
S3
B
EMI
1D5V_S0
CPU JTAG
1D05V_VTT VCCPW RGOOD_0 VCCPW RGOOD_1 51R2J-2-GP DRAMPW ROK 51R2J-2-GP XDP_TDO_M 51R2J-2-GP
1
1
1 1 1 1 1
2
SC22P50V2JN-4GP
NON-S3
2
R164 1K1R2F-GP
DY
2
R717 1K1R2F-GP
XDP_TMS R124 XDP_TDI R473 XDP_PREQ# R129 XDP_TDO R477
DY EC14
2
1 1 1 1
DY DY DY
2 2 1 2 2
51R2J-2-GP XDP_TDI_M
DY EC19
2
SC22P50V2JN-4GP SC22P50V2JN-4GP
H_VTTPW RGD R122 0R0402-PAD PLT_RST#_R
DY EC24
2
DRAMPW ROK
PM_DRAM_PW RGD
DY EC20
2
SC22P50V2JN-4GP SC22P50V2JN-4GP
1
2
NON-S3
2
1
XDP_TCLK R132 XDP_TRST# R480
1 1
DY
2
51R2J-2-GP
2
51R2J-2-GP
3D3V_S5
A
43,50 1D5V_S0_PW RGD
2
R165 3KR2F-GP
S3
R716 750R2F-GP
SM_DRAMRST#
DY EC22
1 2
DY EC34
SC22P50V2JN-4GP
U86
JV70-CP
A
1 2
B A
SB 0817
3
S3
VCC Y
5 4
PM_DRAM_PW RGD_1 Title
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
GND
74LVC1G08GW -1-GP
73.01G08.L04
CPU (2/7)
SB 0814
Size A3 Date: Document Number Thursday, October 08, 2009 Rev
JV70-CP
-1
5 of 68
Sheet
5
4
3
2
1
CPU1D CPU1C 3 OF 9
4
OF 9
AUBURNDALE
AUBURNDALE
21 M_B_DQ[63..0]
20 M_A_DQ[63..0]
D
C
B
M_A_DQ0 M_A_DQ1 M_A_DQ2 M_A_DQ3 M_A_DQ4 M_A_DQ5 M_A_DQ6 M_A_DQ7 M_A_DQ8 M_A_DQ9 M_A_DQ10 M_A_DQ11 M_A_DQ12 M_A_DQ13 M_A_DQ14 M_A_DQ15 M_A_DQ16 M_A_DQ17 M_A_DQ18 M_A_DQ19 M_A_DQ20 M_A_DQ21 M_A_DQ22 M_A_DQ23 M_A_DQ24 M_A_DQ25 M_A_DQ26 M_A_DQ27 M_A_DQ28 M_A_DQ29 M_A_DQ30 M_A_DQ31 M_A_DQ32 M_A_DQ33 M_A_DQ34 M_A_DQ35 M_A_DQ36 M_A_DQ37 M_A_DQ38 M_A_DQ39 M_A_DQ40 M_A_DQ41 M_A_DQ42 M_A_DQ43 M_A_DQ44 M_A_DQ45 M_A_DQ46 M_A_DQ47 M_A_DQ48 M_A_DQ49 M_A_DQ50 M_A_DQ51 M_A_DQ52 M_A_DQ53 M_A_DQ54 M_A_DQ55 M_A_DQ56 M_A_DQ57 M_A_DQ58 M_A_DQ59 M_A_DQ60 M_A_DQ61 M_A_DQ62 M_A_DQ63
A10 C10 C7 A7 B10 D10 E10 A8 D8 F10 E6 F7 E9 B7 E7 C6 H10 G8 K7 J8 G7 G10 J7 J10 L7 M6 M8 L9 L6 K8 N8 P9 AH5 AF5 AK6 AK7 AF6 AG5 AJ7 AJ6 AJ10 AJ9 AL10 AK12 AK8 AL7 AK11 AL8 AN8 AM10 AR11 AL11 AM9 AN9 AT11 AP12 AM12 AN12 AM13 AT14 AT12 AL13 AR14 AP14
SA_CK0 SA_CK0# SA_CKE0
AA6 AA7 P7
M_CLK_DDR0 20 M_CLK_DDR#0 20 M_CKE0 20
SA_DQ0 SA_DQ1 SA_DQ2 SA_DQ3 SA_DQ4 SA_DQ5 SA_DQ6 SA_DQ7 SA_DQ8 SA_DQ9 SA_DQ10 SA_DQ11 SA_DQ12 SA_DQ13 SA_DQ14 SA_DQ15 SA_DQ16 SA_DQ17 SA_DQ18 SA_DQ19 SA_DQ20 SA_DQ21 SA_DQ22 SA_DQ23 SA_DQ24 SA_DQ25 SA_DQ26 SA_DQ27 SA_DQ28 SA_DQ29 SA_DQ30 SA_DQ31 SA_DQ32 SA_DQ33 SA_DQ34 SA_DQ35 SA_DQ36 SA_DQ37 SA_DQ38 SA_DQ39 SA_DQ40 SA_DQ41 SA_DQ42 SA_DQ43 SA_DQ44 SA_DQ45 SA_DQ46 SA_DQ47 SA_DQ48 SA_DQ49 SA_DQ50 SA_DQ51 SA_DQ52 SA_DQ53 SA_DQ54 SA_DQ55 SA_DQ56 SA_DQ57 SA_DQ58 SA_DQ59 SA_DQ60 SA_DQ61 SA_DQ62 SA_DQ63
SA_CK1 SA_CK1# SA_CKE1
Y6 Y5 P6
M_CLK_DDR1 20 M_CLK_DDR#1 20 M_CKE1 20
SA_CS0# SA_CS1#
AE2 AE8
M_CS#0 20 M_CS#1 20
SA_ODT0 SA_ODT1
AD8 AF9
M_ODT0 20 M_ODT1 20
SA_DM0 SA_DM1 SA_DM2 SA_DM3 SA_DM4 SA_DM5 SA_DM6 SA_DM7
B9 D7 H7 M7 AG6 AM7 AN10 AN13
M_A_DM0 M_A_DM1 M_A_DM2 M_A_DM3 M_A_DM4 M_A_DM5 M_A_DM6 M_A_DM7
M_A_DM[7..0] 20
DDR SYSTEM MEMORY A
DDR SYSTEM MEMORY - B
SA_DQS0# SA_DQS1# SA_DQS2# SA_DQS3# SA_DQS4# SA_DQS5# SA_DQS6# SA_DQS7#
C9 F8 J9 N9 AH7 AK9 AP11 AT13
M_A_DQS#0 M_A_DQS#1 M_A_DQS#2 M_A_DQS#3 M_A_DQS#4 M_A_DQS#5 M_A_DQS#6 M_A_DQS#7
M_A_DQS#[7..0] 20
SA_DQS0 SA_DQS1 SA_DQS2 SA_DQS3 SA_DQS4 SA_DQS5 SA_DQS6 SA_DQS7
C8 F9 H9 M9 AH8 AK10 AN11 AR13
M_A_DQS0 M_A_DQS1 M_A_DQS2 M_A_DQS3 M_A_DQS4 M_A_DQS5 M_A_DQS6 M_A_DQS7
M_A_DQS[7..0] 20
20 20 20
M_A_BS0 M_A_BS1 M_A_BS2
AC3 AB2 U7
SA_BS0 SA_BS1 SA_BS2
20 20 20
M_A_CAS# M_A_RAS# M_A_W E#
AE1 AB3 AE9
SA_CAS# SA_RAS# SA_WE#
SA_MA0 SA_MA1 SA_MA2 SA_MA3 SA_MA4 SA_MA5 SA_MA6 SA_MA7 SA_MA8 SA_MA9 SA_MA10 SA_MA11 SA_MA12 SA_MA13 SA_MA14 SA_MA15
Y3 W1 AA8 AA3 V1 AA9 V8 T1 Y9 U6 AD4 T2 U3 AG8 T3 V9
M_A_A0 M_A_A1 M_A_A2 M_A_A3 M_A_A4 M_A_A5 M_A_A6 M_A_A7 M_A_A8 M_A_A9 M_A_A10 M_A_A11 M_A_A12 M_A_A13 M_A_A14 M_A_A15
M_A_A[15..0] 20
M_B_DQ0 M_B_DQ1 M_B_DQ2 M_B_DQ3 M_B_DQ4 M_B_DQ5 M_B_DQ6 M_B_DQ7 M_B_DQ8 M_B_DQ9 M_B_DQ10 M_B_DQ11 M_B_DQ12 M_B_DQ13 M_B_DQ14 M_B_DQ15 M_B_DQ16 M_B_DQ17 M_B_DQ18 M_B_DQ19 M_B_DQ20 M_B_DQ21 M_B_DQ22 M_B_DQ23 M_B_DQ24 M_B_DQ25 M_B_DQ26 M_B_DQ27 M_B_DQ28 M_B_DQ29 M_B_DQ30 M_B_DQ31 M_B_DQ32 M_B_DQ33 M_B_DQ34 M_B_DQ35 M_B_DQ36 M_B_DQ37 M_B_DQ38 M_B_DQ39 M_B_DQ40 M_B_DQ41 M_B_DQ42 M_B_DQ43 M_B_DQ44 M_B_DQ45 M_B_DQ46 M_B_DQ47 M_B_DQ48 M_B_DQ49 M_B_DQ50 M_B_DQ51 M_B_DQ52 M_B_DQ53 M_B_DQ54 M_B_DQ55 M_B_DQ56 M_B_DQ57 M_B_DQ58 M_B_DQ59 M_B_DQ60 M_B_DQ61 M_B_DQ62 M_B_DQ63
B5 A5 C3 B3 E4 A6 A4 C4 D1 D2 F2 F1 C2 F5 F3 G4 H6 G2 J6 J3 G1 G5 J2 J1 J5 K2 L3 M1 K5 K4 M4 N5 AF3 AG1 AJ3 AK1 AG4 AG3 AJ4 AH4 AK3 AK4 AM6 AN2 AK5 AK2 AM4 AM3 AP3 AN5 AT4 AN6 AN4 AN3 AT5 AT6 AN7 AP6 AP8 AT9 AT7 AP9 AR10 AT10
SB_DQ0 SB_DQ1 SB_DQ2 SB_DQ3 SB_DQ4 SB_DQ5 SB_DQ6 SB_DQ7 SB_DQ8 SB_DQ9 SB_DQ10 SB_DQ11 SB_DQ12 SB_DQ13 SB_DQ14 SB_DQ15 SB_DQ16 SB_DQ17 SB_DQ18 SB_DQ19 SB_DQ20 SB_DQ21 SB_DQ22 SB_DQ23 SB_DQ24 SB_DQ25 SB_DQ26 SB_DQ27 SB_DQ28 SB_DQ29 SB_DQ30 SB_DQ31 SB_DQ32 SB_DQ33 SB_DQ34 SB_DQ35 SB_DQ36 SB_DQ37 SB_DQ38 SB_DQ39 SB_DQ40 SB_DQ41 SB_DQ42 SB_DQ43 SB_DQ44 SB_DQ45 SB_DQ46 SB_DQ47 SB_DQ48 SB_DQ49 SB_DQ50 SB_DQ51 SB_DQ52 SB_DQ53 SB_DQ54 SB_DQ55 SB_DQ56 SB_DQ57 SB_DQ58 SB_DQ59 SB_DQ60 SB_DQ61 SB_DQ62 SB_DQ63
SB_CK0 SB_CK0# SB_CKE0 SB_CK1 SB_CK1# SB_CKE1
W8 W9 M3 V7 V6 M2
M_CLK_DDR2 21 M_CLK_DDR#2 21 M_CKE2 21 M_CLK_DDR3 21 M_CLK_DDR#3 21 M_CKE3 21
D
SB_CS0# SB_CS1#
AB8 AD6
M_CS#2 21 M_CS#3 21
SB_ODT0 SB_ODT1
AC7 AD1
M_ODT2 21 M_ODT3 21
SB_DM0 SB_DM1 SB_DM2 SB_DM3 SB_DM4 SB_DM5 SB_DM6 SB_DM7
D4 E1 H3 K1 AH1 AL2 AR4 AT8
M_B_DM0 M_B_DM1 M_B_DM2 M_B_DM3 M_B_DM4 M_B_DM5 M_B_DM6 M_B_DM7
M_B_DM[7..0] 21
SB_DQS0# SB_DQS1# SB_DQS2# SB_DQS3# SB_DQS4# SB_DQS5# SB_DQS6# SB_DQS7#
D5 F4 J4 L4 AH2 AL4 AR5 AR8
M_B_DQS#0 M_B_DQS#1 M_B_DQS#2 M_B_DQS#3 M_B_DQS#4 M_B_DQS#5 M_B_DQS#6 M_B_DQS#7
M_B_DQS#[7..0] 21
C
SB_DQS0 SB_DQS1 SB_DQS2 SB_DQS3 SB_DQS4 SB_DQS5 SB_DQS6 SB_DQS7
C5 E3 H4 M5 AG2 AL5 AP5 AR7
M_B_DQS0 M_B_DQS1 M_B_DQS2 M_B_DQS3 M_B_DQS4 M_B_DQS5 M_B_DQS6 M_B_DQS7
M_B_DQS[7..0] 21
21 21 21 21 21 21
M_B_BS0 M_B_BS1 M_B_BS2 M_B_CAS# M_B_RAS# M_B_W E#
AB1 W5 R7 AC5 Y7 AC6
SB_BS0 SB_BS1 SB_BS2 SB_CAS# SB_RAS# SB_WE#
SB_MA0 SB_MA1 SB_MA2 SB_MA3 SB_MA4 SB_MA5 SB_MA6 SB_MA7 SB_MA8 SB_MA9 SB_MA10 SB_MA11 SB_MA12 SB_MA13 SB_MA14 SB_MA15
U5 V2 T5 V3 R1 T8 R2 R6 R4 R5 AB5 P3 R3 AF7 P5 N1
M_B_A0 M_B_A1 M_B_A2 M_B_A3 M_B_A4 M_B_A5 M_B_A6 M_B_A7 M_B_A8 M_B_A9 M_B_A10 M_B_A11 M_B_A12 M_B_A13 M_B_A14 M_B_A15
M_B_A[15..0] 21
B
AUBURUNF,CLARKU1NF
A
62.10040.611 2ND = 62.10055.321
AUBURUNF,CLARKU1NF
JV70-CP
A
62.10040.611 2ND = 62.10055.321
Title
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C.
CPU (3/7)
Size A3 Date:
5 4 3 2
Document Number Thursday, October 08, 2009
Rev
JV70-CP
-1
6 of 68
1
Sheet
5
4
3
2
1
CPU1F
6
OF 9
VCC_CORE
AUBURNDALE
-1 0929
VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 AH14 AH12 AH11 AH10 J14 J13 H14 H12 G14 G13 G12 G11 F14 F13 F12 F11 E14 E12 D14 D13 D12 D11 C14 C13 C12 C11 B14 B12 A14 A13 A12 A11 C297 SC10U6D3V3MX-GP C571 SC10U6D3V3MX-GP C282 SC10U6D3V3MX-GP C293 SC10U6D3V3MX-GP C292 SC10U6D3V3MX-GP SC10U6D3V3MX-GP C291 SC10U6D3V3MX-GP SC10U6D3V3MX-GP C572 SC10U6D3V3MX-GP
1D05V_VTT
PROCESSOR CORE POWER
VCC_CORE
D
-1 0929
65A
1 1
1
1
1
DY
2
DY
2
DY
2
DY
2
1
C261 SC10U6D3V3MX-GP C196 SC10U6D3V3MX-GP C238 SC10U6D3V3MX-GP
C259 SC10U6D3V3MX-GP C156 SC10U6D3V3MX-GP
C234 SC10U6D3V3MX-GP C231 SC10U6D3V3MX-GP
C203 SC10U6D3V3MX-GP C249 SC10U6D3V3MX-GP
C260 SC10U6D3V3MX-GP
C220 SC10U6D3V3MX-GP SC10U6D3V3MX-GP
1
1
1
1
1
DY
2
DY
2
1
C159 SC10U6D3V3MX-GP
C204 SC10U6D3V3MX-GP SC10U6D3V3MX-GP
1
1
1
1
1
DY
2
1
C176 SC10U6D3V3MX-GP
C264 SC10U6D3V3MX-GP
C237 SC10U6D3V3MX-GP
C221 SC10U6D3V3MX-GP
C171 SC10U6D3V3MX-GP SC10U6D3V3MX-GP
C
1
1
1
1
1
1
C262 SC10U6D3V3MX-GP
C209 SC10U6D3V3MX-GP
C232 SC10U6D3V3MX-GP
C226 SC10U6D3V3MX-GP
C263 SC10U6D3V3MX-GP
C243 SC10U6D3V3MX-GP SC10U6D3V3MX-GP
DY
2
DY
2
DY
2
CPU VIDS
B
A
AG35 AG34 AG33 AG32 AG31 AG30 AG29 AG28 AG27 AG26 AF35 AF34 AF33 AF32 AF31 AF30 AF29 AF28 AF27 AF26 AD35 AD34 AD33 AD32 AD31 AD30 AD29 AD28 AD27 AD26 AC35 AC34 AC33 AC32 AC31 AC30 AC29 AC28 AC27 AC26 AA35 AA34 AA33 AA32 AA31 AA30 AA29 AA28 AA27 AA26 Y35 Y34 Y33 Y32 Y31 Y30 Y29 Y28 Y27 Y26 V35 V34 V33 V32 V31 V30 V29 V28 V27 V26 U35 U34 U33 U32 U31 U30 U29 U28 U27 U26 R35 R34 R33 R32 R31 R30 R29 R28 R27 R26 P35 P34 P33 P32 P31 P30 P29 P28 P27 P26
VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC
1
1
1
1
1
1
DY
DY
DY
1
DY
D
2
2
2
2
2
2
2
2
2
1.1V RAIL POWER
2
2
2
2
The decoupling capacitors, filter recommendations and sense resistors on the CPU/PCH Rails are specific to the CRB Implementation. Customers need to follow the recommendations in the Calpella Platform Design Guide.
-1 0929
AF10 AE10 AC10 AB10 Y10 W10 U10 T10 J12 J11 J16 J15
1D05V_VTT
C
VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0 VTT0
2
2
2
2
2
1
DY
1 2
C289 SC10U6D3V3MX-GP
C294 SC10U6D3V3MX-GP
CPU CORE SUPPLY
2
1D05V_VTT RN18 1 2 SRN0J-10-GP-U 4 3
+VTT_43 +VTT_44
Please note that the VTT Rail Values are Auburndale VTT=1.05V; Clarksfield VTT=1.1V
PSI# VID0 VID1 VID2 VID3 VID4 VID5 VID6 PROC_DPRSLPVR AN33 AK35 AK33 AK34 AL35 AL33 AM33 AM35 AM34 H_VID0 H_VID1 H_VID2 H_VID3 H_VID4 H_VID5 H_VID6 PSI# 45 45
2
2
2
H_VID[6..0]
POWER
B
PM_DPRSLPVR 45
VTT_SELECT
G15
H_VTTVID1
H_VTTVID1 49
Clarksfield H_VTTVID1 = Low, VTT = 1.1V Arrandale H_VTTVID1 = High, VTT = 1.05V
VCC_CORE 1 ISENSE AN35 IMVP_IMON 45 R94 100R2F-L1-GP-U 2
SENSE LINES
VCC_SENSE VSS_SENSE VTT_SENSE VSS_SENSE_VTT
AJ34 AJ35 1 B15 A15 R93 100R2F-L1-GP-U 2
VCC_SENSE 45 VSS_SENSE 45 VTT_SENSE 49 TP90 TPAD14-GP
TP_VSS_SENSE_VTT 1
JV70-CP
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (4/7)
AUBURUNF,CLARKU1NF
62.10040.611 2ND = 62.10055.321
5 4 3 2
Size Custom Date:
Document Number
Rev
JV70-CP
Sheet
1
-1
7 of 68
Thursday, October 08, 2009
5
4
3
2
1
VCC_GFXCORE CPU1G 7 OF 9
SB 0820
D
1
1
2
1
2
1
1
1
ST330U2VBM-GP
UMA_PX UMA_PX UMA_PX UMA_PX
SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP SC10U6D3V3MX-GP
DY
2
DY
2
DY
2
1
TC20
C270 SC10U6D3V3MX-GP
R718 0R3J-0-U-GP
C254 SC10U6D3V3MX-GP
R720 0R3J-0-U-GP
C273 SC10U6D3V3MX-GP SC10U6D3V3MX-GP
C266
C268
C257
GRAPHICS VIDs
77.23371.27L 2ND = 80.3371V.12L
For Graphics Disable , Can be connected to GND directly
- 1.5V RAILS
C
AT21 AT19 AT18 AT16 AR21 AR19 AR18 AR16 AP21 AP19 AP18 AP16 AN21 AN19 AN18 AN16 AM21 AM19 AM18 AM16 AL21 AL19 AL18 AL16 AK21 AK19 AK18 AK16 AJ21 AJ19 AJ18 AJ16 AH21 AH19 AH18 AH16
VAXG1 VAXG2 VAXG3 VAXG4 VAXG5 VAXG6 VAXG7 VAXG8 VAXG9 VAXG10 VAXG11 VAXG12 VAXG13 VAXG14 VAXG15 VAXG16 VAXG17 VAXG18 VAXG19 VAXG20 VAXG21 VAXG22 VAXG23 VAXG24 VAXG25 VAXG26 VAXG27 VAXG28 VAXG29 VAXG30 VAXG31 VAXG32 VAXG33 VAXG34 VAXG35 VAXG36
AUBURNDALE
SENSE LINES
VAXG_SENSE VSSAXG_SENSE
AR22 AT22
VCC_AXG_SENSE 52 VSS_AXG_SENSE 52
GFX_IMON For Graphics Disable , Pull-down to GND via 1-k ± 5% resistor
D
2
2
2
GFX_VR_EN GFX_DPRSLPVR GFX_IMON
AR25 AT25 AM24 1 R139 2 1KR2J-1-GP
GFX_VR_EN 52 GFX_DPRSLPVR 52 GFX_IMON 52
R708 0R3J-0-U-GP
R707 0R3J-0-U-GP
R706 0R3J-0-U-GP
2 1
1
1
DIS-ONLY
VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ VDDQ AJ1 AF1 AE7 AE4 AC1 AB7 AB4 Y1 W7 W4 U1 T7 T4 P1 N7 N4 L1 H1 1 1 1 1
6A
1 1 1
C303 SC1U6D3V2KX-GP C309 SC1U6D3V2KX-GP
1
C307 DY SC1U6D3V2KX-GP
C312 SC1U6D3V2KX-GP
DY
DY
1
2
2
2
2
2
2
2
2
1
POWER
S3
13,20 PM_SLP_S3_CTL
D
2
Please note that the VTT Rail Values are Auburndale VTT=1.05V; Clarksfield VTT=1.1V
DDR3
1
1
C250 SC10U6D3V3MX-GP
C240 SC1U6D3V2KX-GP SC1U6D3V2KX-GP
VTT1 VTT1 VTT1 VTT1
P10 N10 L10 K10 1
C283 SC1U6D3V2KX-GP
2
2
1D05V_VTT
1
C295 SC10U6D3V3MX-GP
S
2
1.1V
1
1
1
1
B
ST330U2VBM-GP
DY
1
TC21
C269 SC10U6D3V3MX-GP
C275 SC10U6D3V3MX-GP
C277 SC10U6D3V3MX-GP SC10U6D3V3MX-GP
DY
2 2
C255
77.23371.27L 2ND = 80.3371V.12L
1.8V
K26 J27 J26 J25 H27 G28 G27 G26 F26 E26 E25
VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1 VTT1
VTT1 VTT1 VTT1 VTT1 VTT1 VTT1
J22 J20 J18 H21 H20 H19
2
2
2
2
1
C248 SC1U6D3V2KX-GP
DY C253
SC10U6D3V3MX-GP
2
VTT1 VTT1 VTT1
L26 L27 M26
2
1
1
1
1
1
C246 SC1U6D3V2KX-GP AUBURUNF,CLARKU1NF
C247 SC1U6D3V2KX-GP
C151 SC4D7U6D3V3KX-GP
2
2
2
2
62.10040.611 2ND = 62.10055.321
2
1
DIS-ONLY
DIS-ONLY
GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6
AM22 AP22 AN22 AP23 AM23 AP24 AN24
GFX_VID0 GFX_VID1 GFX_VID2 GFX_VID3 GFX_VID4 GFX_VID5 GFX_VID6
2
2
2
1
1
2
1D5V_S3 GFX_VID[6..0] 52
GRAPHICS
NON-S3 NON-S3 NON-S3 NON-S3
R705 0R3J-0-U-GP 1D5V_S0
C354 SC10U6D3V3MX-GP SC10U6D3V3MX-GP
C343 SC10U6D3V3MX-GP
C353 SC10U6D3V3MX-GP
C352 SC10U6D3V3MX-GP
S3
R857 220R2F-GP
C
1D05V_VTT
Q44 2N7002-11-GP
G
J24 J23 H25
VTT1 VTT1 VTT1
84.27002.W31 2nd = 84.27002.N31
FDI FDI
SB 0814
1D05V_VTT
21A
1D05V_VTT
B
PEG & DMI PEG & DMI
SC1U6D3V2KX-GP
+V1.8S_VCCSFR
0.6A
C241 SC10U6D3V3MX-GP C155 SC10U6D3V3MX-GP
1D8V_S0
1 R82 2 0R0603-PAD
DY
A
JV70-CP
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (5/7)
Size A3 Date:
5 4 3 2
Document Number
Rev
JV70-CP
Thursday, October 08, 2009 Sheet
1
-1
8 of 68
5
4
3
2
1
CPU1H
8
OF 9
CPU1I
9
OF 9
D
C
B
AT20 AT17 AR31 AR28 AR26 AR24 AR23 AR20 AR17 AR15 AR12 AR9 AR6 AR3 AP20 AP17 AP13 AP10 AP7 AP4 AP2 AN34 AN31 AN23 AN20 AN17 AM29 AM27 AM25 AM20 AM17 AM14 AM11 AM8 AM5 AM2 AL34 AL31 AL23 AL20 AL17 AL12 AL9 AL6 AL3 AK29 AK27 AK25 AK20 AK17 AJ31 AJ23 AJ20 AJ17 AJ14 AJ11 AJ8 AJ5 AJ2 AH35 AH34 AH33 AH32 AH31 AH30 AH29 AH28 AH27 AH26 AH20 AH17 AH13 AH9 AH6 AH3 AG10 AF8 AF4 AF2 AE35
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
VSS
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AE34 AE33 AE32 AE31 AE30 AE29 AE28 AE27 AE26 AE6 AD10 AC8 AC4 AC2 AB35 AB34 AB33 AB32 AB31 AB30 AB29 AB28 AB27 AB26 AB6 AA10 Y8 Y4 Y2 W35 W34 W33 W32 W31 W30 W29 W28 W27 W26 W6 V10 U8 U4 U2 T35 T34 T33 T32 T31 T30 T29 T28 T27 T26 T6 R10 P8 P4 P2 N35 N34 N33 N32 N31 N30 N29 N28 N27 N26 N6 M10 L35 L32 L29 L8 L5 L2 K34 K33 K30
AUBURNDALE
K27 K9 K6 K3 J32 J30 J21 J19 H35 H32 H28 H26 H24 H22 H18 H15 H13 H11 H8 H5 H2 G34 G31 G20 G9 G6 G3 F30 F27 F25 F22 F19 F16 E35 E32 E29 E24 E21 E18 E13 E11 E8 E5 E2 D33 D30 D26 D9 D6 D3 C34 C32 C29 C28 C24 C22 C20 C19 C16 B31 B25 B21 B18 B17 B13 B11 B8 B6 B4 A29 A27 A23 A9
VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS
AUBURNDALE
D
C
VSS
AR34 B34 B2 B1 A35 AT1 AT35 AT33 AT34 AP35 AR35 AT3 AR1 AP1 AT2 C1 A3 C35 B35 A34 A33
TP_MCP_VSS_NCTF6 TP_MCP_VSS_NCTF1 TP_MCP_VSS_NCTF2 TP_MCP_VSS_NCTF7
NCTF TEST PIN: A35,AT1,AT35,B1,A3,A33,A34,AP1,AP35, AR1,AR35,AT2,AT3,AT33,AT34,B35,C1,C35
VSS_NCTF#AR34 VSS_NCTF#B34 VSS_NCTF#B2 VSS_NCTF#B1 VSS_NCTF#A35 VSS_NCTF#AT1 VSS_NCTF#AT35 RSVD_NCTF#AT33 RSVD_NCTF#AT34 RSVD_NCTF#AP35 RSVD_NCTF#AR35 RSVD_NCTF#AT3 RSVD_NCTF#AR1 RSVD_NCTF#AP1 RSVD_NCTF#AT2 RSVD_NCTF#C1 RSVD_NCTF#A3 RSVD_NCTF#C35 RSVD_NCTF#B35 RSVD_NCTF#A34 RSVD_NCTF#A33
1 1 1 1
TP91 TP26 TP92 TP85
AFTE14P-GP AFTE14P-GP AFTE14P-GP AFTE14P-GP
B
AUBURUNF,CLARKU1NF
AUBURUNF,CLARKU1NF
62.10040.611 2ND = 62.10055.321
A
62.10040.611 2ND = 62.10055.321
JV70-CP
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (6/7)
Size A3 Date:
5 4 3 2
Document Number
Rev
JV70-CP
Thursday, October 08, 2009 Sheet
1
-1
9 of 68
5
4
3
2
1
CPU1E
D
5
OF 9
D
AUBURNDALE
RSVD#AJ13 RSVD#AJ12 RSVD#AH25 RSVD#AK26 RSVD#AL26 RSVD_NCTF#AR2 RSVD#AJ26 RSVD#AJ27
1
AJ13 AJ12 AH25 AK26 AL26 AR2 AJ26 AJ27
CFG0 R118 3KR2F-GP
PCI-Express Configuration Select
DY
2
SO-DIMM VREFDQ (M3) Circuit for Clarksfield Processor
RN15 20 SA_DIMM_VREF# 21 SB_DIMM_VREF#
DY
4 3
H_RSVD9_R H_RSVD10_R
1 2
SRN0J-10-GP-U
SB 0814
AP25 AL25 AL24 AL22 AJ33 AG9 M27 L28 J17 H17 G25 G17 E31 E30
RSVD#AP25 RSVD#AL25 RSVD#AL24 RSVD#AL22 RSVD#AJ33 RSVD#AG9 RSVD#M27 RSVD#L28 SA_DIMM_VREF# SB_DIMM_VREF# RSVD#G25 RSVD#G17 RSVD#E31 RSVD#E30
CFG0
1:Single PEG 0:Bifurcation enabled
CFG3
CFG3 - PCI-Express Static Lane Reversal
1
R95 3KR2F-GP
CFG3
1
TPAD14-GP TPAD14-GP
C
TP41 TP31 TP32 TP37 TP28 TP33 TP42 TP40 TP38 TP34 TP29 TP39 TP36 TP35
1 1 1 1 1 1 1 1 1 1 1 1 1 1
TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP TPAD14-GP
RESERVED
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17
RSVD64_R RSVD65_R
1 1
R733 2 0R0402-PAD R734 2 0R0402-PAD
1
AM30 AM28 AP31 AL32 AL30 AM31 AN29 AM32 AK32 AK31 AK28 AJ28 AN30 AN32 AJ32 AJ29 AJ30 AK30 H16
CFG0 CFG1 CFG2 CFG3 CFG4 CFG5 CFG6 CFG7 CFG8 CFG9 CFG10 CFG11 CFG12 CFG13 CFG14 CFG15 CFG16 CFG17 RSVD_TP#H16
RSVD#AL28 RSVD#AL29 RSVD#AP30 RSVD#AP32 RSVD#AL27 RSVD#AT31 RSVD#AT32 RSVD#AP33 RSVD#AR33
RSVD#AR32 RSVD_TP#E15 RSVD_TP#F15 KEY RSVD#D15 RSVD#C15 RSVD#AJ15 RSVD#AH15
AR32 E15 F15 A2 D15 C15 AJ15 AH15
CFG7 R99 3KR2F-GP
2
AL28 AL29 AP30 AP32 AL27 AT31 AT32 AP33 AR33
CFG4 R102 3KR2F-GP
2
1 :Normal Operation 0 :Lane Numbers Reversed 15 -> 0, 14 -> 1, ...
CFG4 - Display Port Presence
DY
CFG4
1:Disabled; No Physical Display Port attached to Embedded Display Port 0:Enabled; An external Display Port device is connected to the Embedded Display Port
C
CFG7(Reserved) - Temporarily used for early Clarksfield samples. CFG7 Clarksfield (only for early samples pre-ES1) Connect to GND with 3.01K Ohm/5% resistor. Note: Only temporary for early CFD sample (rPGA/BGA) [For details please refer to the WW33 MoW and sighting report]. For a common M/B design (for AUB and CFD), the pull-down resistor shouble be used. Does not impact AUB functionality.
DY
2
B19 A19 1 1
R731 2 0R0402-PAD R732 2 0R0402-PAD H_RSVD17_R H_RSVD18_R
RSVD#B19 RSVD#A19 RSVD#A20 RSVD#B20 RSVD#U9 RSVD#T9 RSVD#AC9 RSVD#AB9 RSVD_TP#AA5 RSVD_TP#AA4 RSVD_TP#R8 RSVD_TP#AD3 RSVD_TP#AD2 RSVD_TP#AA2 RSVD_TP#AA1 RSVD_TP#R9 RSVD_TP#AG7 RSVD_TP#AE3 RSVD_TP#V4 RSVD_TP#V5 RSVD_TP#N2 RSVD_TP#AD5 RSVD_TP#AD7 RSVD_TP#W3 RSVD_TP#W2 RSVD_TP#N3 RSVD_TP#AE5 RSVD_TP#AD9 VSS
A20 B20 U9 T9
B
AC9 AB9
AA5 AA4 R8 AD3 AD2 AA2 AA1 R9 AG7 AE3 V4 V5 N2 AD5 AD7 W3 W2 N3 AE5 AD9 AP34
B
J29 J28
RSVD#J29 RSVD#J28
VSS (AP34) can be left NC is CRB implementation; EDS/DG recommendation to GND.
RSVD_VSS 1
R92 2 0R0402-PAD
AUBURUNF,CLARKU1NF
62.10040.611
A
BOM change to 62.10055.321
2ND = 62.10053.561 3RD = 62.10055.341
JV70-CP
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
CPU (7/7)
Size A3 Date:
5 4 3 2
Document Number Thursday, October 08, 2009
Rev
JV70-CP
-1
10 of 68
1
Sheet
5
4
3
2
1
RTC_AUX_S5 ICH_RTCX1 RTC_AUX_S5 RN57
integrated VccSus1_05,VccSus1_5,VccCL1_5
1 2 R542 10MR2J-L-GP
ICH_RTCX2
INTVRMEN
4 3 1
C622 SC1U6D3V2KX-GP
1 2
SRN20KJ-GP-U
1 2 R539 1MR2J-1-GP 1 2 R534 330KR2F-L-GP
SM_INTRUDER#
High=Enable High=Enable
Low=Disable Low=Disable
X6
ICH_INTVRMEN
INTVRMEN- Integrated SUS 1.1V VRM Enable High - Enable internal VRs
PCH1A 1 OF 10
integrated VccLan1_05VccCL1_05
LAN100_SLP
1
C628 SC15P50V2JN-2-GP SC15P50V2JN-2-GP
1
D
C627 SC15P50V2JN-2-GP
SC 0901
2
4
1
D
3 2
2 2
ICH_RTCX1 ICH_RTCX2 ICH_RTCRST#
B13 D13 C14 D17 A16 A14
RTCX1 RTCX2 RTCRST#
X-32D768KHZ-46GP
FWH0/LAD0 FWH1/LAD1 FWH2/LAD2 FWH3/LAD3 FWH4/LFRAME#
D33 B33 C32 A32 C34 A34 F34 AB9
PCH_GPIO23 INT_SERIRQ
LPC_LAD0 LPC_LAD1 LPC_LAD2 LPC_LAD3
39,40 39,40 39,40 39,40
82.30001.861
2
SRTCRST# new signal Pin SRTCRST# G39 GAP-OPEN SM_INTRUDER# ICH_INTVRMEN
LPC_LFRAME# 39,40
RTC
LPC
2nd = 82.30001.691
C626 SC1U6D3V2KX-GP
SRTCRST# INTRUDER# INTVRMEN LDRQ0# LDRQ1#/GPIO23 SERIRQ
1
1
TP55 TPAD14-GP INT_SERIRQ 16,39
2 1
R860 32 ACZ_SDATAOUT_AUDIO
1
2
68R2-GP RN72
SC 0901
8 7 6 5
ACZ_RST# ACZ_SYNC ACZ_BIT_CLK ACZ_SDATAOUT
ACZ_BIT_CLK ACZ_SYNC 32 ACZ_SPKR ACZ_RST#
A30 D29 P1 C30 G30 F30
HDA_BCLK HDA_SYNC SPKR HDA_RST# HDA_SDIN0 HDA_SDIN1 HDA_SDIN2 HDA_SDIN3 HDA_SDO HDA_DOCK_EN#/GPIO33 HDA_DOCK_RST#/GPIO13 SATA1RXN SATA1RXP SATA1TXN SATA1TXP SATA0RXN SATA0RXP SATA0TXN SATA0TXP
32 ACZ_RST#_AUDIO 32 ACZ_SYNC_AUDIO 32 ACZ_BITCLK_AUDIO
1 2 3 4
AK7 AK6 AK11 AK9 AH6 AH5 AH9 AH8 AF11 AF9 AF7 AF6 AH3 AH1 AF3 AF1 AD9 AD8 AD6 AD5 AD3 AD1 AB3 AB1
SATA_RXN0 SATA_RXP0 SATA_TXN0 SATA_TXP0
26 26 26 26
HDD
SRN33J-7-GP RN71
C
32 ACZ_SDATAIN0 35 ACZ_SDATAIN1
F32
ACZ_SDATAOUT R518 2 0R0402-PAD HDA_DOCK_EN#
IHDA
35 35 35 35
ACZ_RST#_MDC ACZ_SYNC_MDC ACZ_BTCLK_MDC ACZ_SDATAOUT_MDC
4 3 2 1
5 6 7 8
SRN33J-7-GP
TPAD14-GP
TP54
1
HDA_SDIN2
E32
SATA2RXN SATA2RXP SATA2TXN SATA2TXP SATA3RXN SATA3RXP SATA3TXN SATA3TXP
C
B29 H32 J30
SATA
NO REBOOT STRAP
3D3V_S0
39 ME_UNLOCK#
1
EMI
2 DY 1KR2J-1-GP
ACZ_SPKR EC79 ACZ_SDATAOUT_AUDIO 1 2 DY SC22P50V2JN-4GP
1 R519
DY
2 8K2R2J-3-GP
PCH_JTAG_TCK PCH_JTAG_TMS PCH_JTAG_TDI
SATA4RXN SATA4RXP SATA4TXN SATA4TXP SATA5RXN SATA5RXP SATA5TXN SATA5TXP
SATA_RXN4 SATA_RXP4 SATA_TXN4 SATA_TXP4
27 27 27 27
ODD
1 R560
M3 K3 K1 J2 J4
JTAG_TCK JTAG_TMS JTAG_TDI
PCH_JTAG_TDO
JTAG
No Reboot Strap R23 Low = Default HDA_SPKR High = No Reboot
1D05V_S0
JTAG_TDO TRST#
SATAICOMPO SATAICOMPI
AF16 AF15
SATAICOMP
SPI_CS0#, SPI_MISO, SPI_MOSI, SPI_CLK: No series resistor required if routing length is 1.5"-6.5"
40 PCH_SPI_CLK PCH_SPI_CLK PCH_SPI_CS#0
PCH_JTAG_RST#
1 2 R179 37D4R2F-GP
1 1
R545 2 0R0402-PAD R548 2 0R0402-PAD
SPI_CLK_R SPI_CS#0_R
BA2 AV3 AY3
SPI_CLK SPI_CS0# SPI_CS1# SPI_MOSI SPI_MISO
IBEXPEAK-M-GP-NF
B
B
40
PCH_SPI_CS#0
SB 0814
PCH_JTAG_TMS 1 R556 PCH_JTAG_TDO 1 R554 PCH_JTAG_TDI R559 PCH_JTAG_RST# 1 R217
SATALED# SATA0GP/GPIO21 SATA1GP/GPIO19
T3 Y9 V1
SATA_LED# SATA_DET#0_R SATA_DET#1_R
SATA_LED# 42 SATA_DET#0_R 16
3D3V_S5 40 PCH_SPI_MOSI PCH_SPI_MOSI
1
R543 2 0R0402-PAD
SPI_MOSI_R SPI_MOSO_R
AY1 AV1
200R2J-L1-GP
40 SPI_MOSO_R
2
200R2J-L1-GP
1
2
200R2J-L1-GP
DY
2
10KR2J-3-GP
SPI_MOSI Enable iTPM: Connect to Vcc3_3 with 8.2-k weak pull-up resistor. Disable iTPM: Left floating, no pull-down required
16 PSW _CLR# 16 PCH_GPIO39 PSW _CLR# SATA_DET#1_R PCH_GPIO39 SATA_LED#
SPI
2
RN66
3D3V_S0
PCH_JTAG_TMS 1 R557 PCH_JTAG_TDO 1 R555 PCH_JTAG_TDI R558
A
2
100R2J-2-GP
3D3V_S0
3D3V_AUX_S5
5 6 7 8
SRN10KJ-7GP
4 3 2 1
2
100R2J-2-GP
1 R203
DY
SPI_MOSI_R 2 8K2R2J-3-GP
RTC_AUX_S5
D11
RTC_BAT
2
RTC1
1
2 1
100R2J-2-GP
1 R283 2 0R0603-PAD
RTC_PW R_L
3 1
RTC_PW R
2
PCH_JTAG_RST# 1 R216 PCH_JTAG_TCK 1 R570
DY
2
51R2F-2-GP
C433 SC1U10V2ZY-GP BAS40CW -GP
1 2 R280 1KR2J-1-GP
1 2 NP1 NP2
2
51R2F-2-GP
83.00040.E81 2nd = 83.00040.Q81
PWR GND NP1 NP2
JV70-CP
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
BAT-CON2-1-GP-U
When unused all JTAG pins may be NC
62.70001.011 2ND = 62.70001.041
PCH (1/9) ES2 PCH verison
5 4 3 2
Size A3 Date:
Document Number Thursday, October 08, 2009
Rev
JV70-CP
-1
11 of 68
1
Sheet
5
4
3
2
1
3D3V_S5
8 7 6 5
RN63 SRN2K2J-2-GP KBC_SCL1
3D3V_S0
PCH1B 30 30 30 30 37 37 37 37 PCIE_RXN1 PCIE_RXP1 PCIE_TXN1 PCIE_TXP1 PCIE_RXN2 PCIE_RXP2 PCIE_TXN2 PCIE_TXP2 PCIE_RXN1 PCIE_RXP1 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2 PCIE_RXN2 PCIE_RXP2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2
2 OF 10
2 B9 H14 C8 J14 C6 G8 M14 E10 G12 T13 T11 T9
PCH_GPIO11 SMB_CLK_1 R209 2 0R0402-PAD SMB_DATA_1 1 R201 2 0R0402-PAD
LAN
D
1 C302 1 C308
TXN1 TXP1
BG30 BJ30 BF29 BH29 AW30 BA30 BC30 BD30 AU30 AT30 AU32 AV32 BA32 BB32 BD32 BE32 BF33 BH33 BG32 BJ32 BA34 AW34 BC34 BD34 AT34 AU34 AU36 AV36
PERN1 PERP1 PETN1 PETP1 PERN2 PERP2 PETN2 PETP2 PERN3 PERP3 PETN3 PETP3 PERN4 PERP4 PETN4 PETP4
SMBALERT#/GPIO11 SMBCLK SMBDATA SML0ALERT#/GPIO60 SML0CLK
DY
1 1
SMB_CLK 37 SMB_DATA 37 PEG_CLKREQ#
R565 10KR2J-3-GP
1 2 3 4
SML0_CLK
D
MINICARD1
KBC_SDA1 PCH_GPIO60 SML0_CLK SML0_DATA PCH_GPIO74 KBC_SCL1 KBC_SDA1 CL_CLK TP56 TPAD14-GP TP58 TPAD14-GP TP60 TPAD14-GP 3,20,21 PCH_SMBDATA Q32 KBC_SCL1 39 KBC_SDA1 39 SMB_CLK SMB_DATA 3D3V_S5 3D3V_S0
SML0_DATA
1 C299 1 C301
TXN2 TXP2
SMBus
SML0DATA SML1ALERT#/GPIO74 SML1CLK/GPIO58 SML1DATA/GPIO75
8 7 6 5
RN60 SRN2K2J-2-GP 3D3V_S0
PCI-E*
Controller
Link
PERN5 PERP5 PETN5 PETP5 PERN6 PERP6 PETN6 PETP6 PERN7 PERP7 PETN7 PETP7 PERN8 PERP8 PETN8 PETP8 CLKOUT_PCIE0N CLKOUT_PCIE0P
CL_CLK1 CL_DATA1 CL_RST1#
1
CL_DATA 1 CL_RST# 1
1 2 3 4
1 2
6 5 4
2N7002KDW -GP
SMB_DATA
PEG_A_CLKRQ#/GPIO47 CLKOUT_PEG_A_N CLKOUT_PEG_A_P
H1 AD43 AD45 AN4 AN2 AT1 AT3 AW24 BA24 AP3 AP1 F18 E18 AH13 AH12 P41 J42 AH51 AH53 AF38 T45 P43 T42
PEG_CLKREQ# 1 R553 CLK_PCH_PEGA_N CLK_PCH_PEGA_P CLK_EXP_N CLK_EXP_P CLKOUT_DP_N CLKOUT_DP_P CLKIN_DMI# CLKIN_DMI CLK_CPU_BCLK# CLK_CPU_BCLK DREFCLK# DREFCLK CLK_PCIE_SATA# CLK_PCIE_SATA CLK_ICH14 CLK_PCI_FB XTAL25_IN XTAL25_OUT XCLK_RCOMP
DY
2 0R2J-2-GP 1 1 1 1
ATI_CLKREQ 59 CLK_PCIE_PEG# 58 CLK_PCIE_PEG 58 PEG_CLK#_R 5 PEG_CLK_R 5 SMB_CLK
3
PCH_SMBCLK 3,20,21
R147 2 0R0402-PAD R148 2 0R0402-PAD R552 2 0R0402-PAD R551 2 0R0402-PAD
C
84.2N702.A3F 2ND = 84.DM601.03F
C
BG34 BJ34 BG36 BJ36
TPAD14-GP TPAD14-GP TP49 TP52
PEG
CLKOUT_DMI_N CLKOUT_DMI_P CLKOUT_DP_N/CLKOUT_BCLK1_N CLKOUT_DP_P/CLKOUT_BCLK1_P
From CLK BUFFER
1 1
CLK_PCH_SRC0_N CLK_PCH_SRC0_P PCIE_CLK_RQ0#
AK48 AK47 P9 AM43 AM45 U4 AM47 AM48
1 DY R562 2 0R2J-2-GP 1 DY R563 2 0R2J-2-GP
CLKIN_DMI# 3 CLKIN_DMI 3 CLK_CPU_BCLK# 3 CLK_CPU_BCLK 3 DREFCLK# 3 DREFCLK 3
-1 0929
DPLL_REF_SSCLK# 5 DPLL_REF_SSCLK 5 R566 PEG_CLKREQ#
PCIECLKRQ0#/GPIO73 CLKOUT_PCIE1N CLKOUT_PCIE1P PCIECLKRQ1#/GPIO18 CLKOUT_PCIE2N CLKOUT_PCIE2P PCIECLKRQ2#/GPIO20 CLKOUT_PCIE3N CLKOUT_PCIE3P PCIECLKRQ3#/GPIO25 CLKOUT_PCIE4N CLKOUT_PCIE4P PCIECLKRQ4#/GPIO26 CLKOUT_PCIE5N CLKOUT_PCIE5P PCIECLKRQ5#/GPIO44 CLKOUT_PEG_B_N CLKOUT_PEG_B_P PEG_B_CLKRQ#/GPIO56
IBEXPEAK-M-GP-NF
CLKIN_DMI_N CLKIN_DMI_P CLKIN_BCLK_N CLKIN_BCLK_P CLKIN_DOT_96N CLKIN_DOT_96P CLKIN_SATA_N/CKSSCD_N CLKIN_SATA_P/CKSSCD_P REFCLK14IN CLKIN_PCILOOPBACK XTAL25_IN XTAL25_OUT XCLK_RCOMP CLKOUTFLEX0/GPIO64
1
2
10KR2J-3-GP
37 CLK_PCIE_MINI1# 37 CLK_PCIE_MINI1 37 MINI1_CLKREQ#
1 1 1
R150 2 0R0402-PAD R149 2 0R0402-PAD
CLK_PCH_SRC1_N CLK_PCH_SRC1_P PCIE_CLK_RQ1#
R227 2 0R0402-PAD
3D3V_S5
RN28 CLK_PCIE_SATA# 3 CLK_PCIE_SATA 3 CLK_ICH14 3 CLK_PCI_FB 15 PCH_GPIO74 PCH_GPIO60 PCH_GPIO11
PCIE_CLK_RQ2# R39 R35 0R0402-PAD 2 0R0402-PAD 2 CLK_PCH_SRC3_N CLK_PCH_SRC3_P PCIE_CLK_RQ3#
N4 AH42 AH41 A8 AM51 AM53
1 2 3 4
SRN10KJ-7GP
8 7 6 5
30 CLK_PCIE_LAN# 30 CLK_PCIE_LAN
B
1 1 1
30 LAN_CLKREQ#
R547 2 0R0402-PAD
B
SB 0813
1 R156 2 90D9R2F-1-GP
1D05V_S0 XTAL25_IN 1 R495
PCIE_CLK_RQ4#
M9 AJ50 AJ52
PCIECLKRQ{0,3,4,5,6,7}# should have a 10K pull-up to +3VALW. PCIECLKRQ{1,2} should have a 10K pull-up to +1.05VS (But CRB is pull-up to +3VS).
PCIE_CLK_RQ5#
2
0R2J-2-GP
DIS-ONLY
Clock Flex
H6 AK53 AK51
CLKOUTFLEX1/GPIO65 CLKOUTFLEX2/GPIO66 CLKOUTFLEX3/GPIO67
C607 XTAL25_IN
UMA_PX
2 2 1
1
PEG_B_CLKRQ#
P13
N50
CLK48 33R2J-2-GP
1
2
R491
CLK48_Cardreader 36 C601 SC4D7P50V2CN-1GP
1
R696 1MR2J-1-GP
2
2
2
2
XTAL25_OUT
1
3D3V_S0
3D3V_S5
3D3V_S0
DY
UMA_PX
UMA_PX 82.30020.971 2ND = 82.30020.791 3RD = 82.30005.851
1
X5
SC6D8P50V2DN-GP
XTAL-25MHZ-113-GP C606
R229 10KR2J-3-GP
A
R546 10KR2J-3-GP
R561 10KR2J-3-GP
2 XTAL25_OUT_1 R697 0R2J-2-GP SC 0915
2
2
1
SC6D8P50V2DN-GP
UMA_PX
UMA_PX
A
3D3V_S5 RN29
1
1
1
PCIE_CLK_RQ1#
PCIE_CLK_RQ3#
PCIE_CLK_RQ2#
R228
R544
1 2 3 4
SRN10KJ-7GP
8 7 6 5
PEG_B_CLKRQ# PCIE_CLK_RQ0# PCIE_CLK_RQ4# PCIE_CLK_RQ5#
JV70-CP
1
1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
DY 10KR2J-3-GP
2
DY 10KR2J-3-GP
2
PCH (2/9)
Size A3
5 4 3 2
Document Number
Rev
JV70-CP
Thursday, October 08, 2009
-1
12 of 68
Date:
1 Sheet
5
4
3
2
1
PCH1C 4 4 4 4 4 4 4 4
D
3 OF 10
DMI_RXN0 DMI_RXN1 DMI_RXN2 DMI_RXN3 DMI_RXP0 DMI_RXP1 DMI_RXP2 DMI_RXP3 DMI_TXN0 DMI_TXN1 DMI_TXN2 DMI_TXN3 DMI_TXP0 DMI_TXP1 DMI_TXP2 DMI_TXP3
BC24 BJ22 AW20 BJ20 BD24 BG22 BA20 BG20 BE22 BF21 BD20 BE18 BD22 BH21 BC20 BD18 BH25
DMI0RXN DMI1RXN DMI2RXN DMI3RXN DMI0RXP DMI1RXP DMI2RXP DMI3RXP DMI0TXN DMI1TXN DMI2TXN DMI3TXN DMI0TXP DMI1TXP DMI2TXP DMI3TXP DMI_ZCOMP DMI_IRCOMP
FDI_RXN0 FDI_RXN1 FDI_RXN2 FDI_RXN3 FDI_RXN4 FDI_RXN5 FDI_RXN6 FDI_RXN7 FDI_RXP0 FDI_RXP1 FDI_RXP2 FDI_RXP3 FDI_RXP4 FDI_RXP5 FDI_RXP6 FDI_RXP7 FDI_INT FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1
BA18 BH17 BD16 BJ16 BA16 BE14 BA14 BC12 BB18 BF17 BC16 BG16 AW16 BD14 BB14 BD12 BJ14 BF13 BH13 BJ12 BG14
FDI_TXN0 FDI_TXN1 FDI_TXN2 FDI_TXN3 FDI_TXN4 FDI_TXN5 FDI_TXN6 FDI_TXN7 FDI_TXP0 FDI_TXP1 FDI_TXP2 FDI_TXP3 FDI_TXP4 FDI_TXP5 FDI_TXP6 FDI_TXP7 FDI_INT 4
4 4 4 4 4 4 4 4 4 4 4 4 4 4 4 4
D
4 4 4 4 4 4 4 4 1D05V_S0
DMI
FDI
FDI_FSYNC0 FDI_FSYNC1 FDI_LSYNC0 FDI_LSYNC1
4 4 4 4
1 R531
DMI_IRCOMP_R 2 49D9R2F-GP 3D3V_S0
BF25
1
R230 10KR2J-3-GP
2
PM_SYSRST#_R
T6 M6
SYS_RESET# SYS_PWROK PWROK MEPWROK LAN_RST# DRAMPWROK RSMRST#
WAKE# CLKRUN#/GPIO32
J12 Y1
PCIE_W AKE# PM_CLKRUN#
PCIE_W AKE# 30,37
C
43 PM_PW ROK 43,45 CORE_PW RGD
R220 1
DY
2 0R2J-2-GP B17 K5 A10 D9
PM_RSMRST# R575 2 1 0R0402-PAD SUS_PW R_DN_ACK_R PM_PW RBTN#_R AC_PRESENT_R PCH_GPIO72
PM_CLKRUN# 39
C
43,45,47,48,49,50
R221 2 PM_PW ROK_1 1 0R0402-PAD R212 2 1 2 1 R206 10KR2J-3-GP 0R0402-PAD ME_PW ROK ALL_PW RGD 1 DY 2 0R2J-2-GP ALL_PW RGD R222 LAN_RST#1 1 2 R192 10KR2J-3-GP PM_DRAM_PW RGD
System Power Management
SUS_STAT#/GPIO61 SUSCLK/GPIO62 SLP_S5#/GPIO63 SLP_S4# SLP_S3# SLP_M# TP23 PMSYNCH SLP_LAN#/GPIO29
P8 F3 E4 H7 P12 K8 N2 BJ10 F6
PM_SUS_STAT# 1 PM_SUS_CLK PM_SLP_S5# PM_SLP_S4#_R PM_SLP_S3#_R PM_SLP_M#_R PM_SLP_DSW # H_PM_SYNC PM_SLP_LAN#
TP59 TPAD14-GP TP66 TPAD14-GP TP65 TPAD14-GP R205 2 0R0402-PAD
1 1
5 PM_DRAM_PW RGD
C16 M1 P5 P7 A6 F14
1
PM_SLP_S4# 39,48,50 PM_SLP_S3# 33,39,43,48,49,50,52 PM_SLP_M# 39
39 SUS_PW R_DN_ACK 39,56 PM_PW RBTN# 39 AC_PRESENT
SUS_PWR_DN_ACK/GPIO30 PWRBTN# ACPRESENT/GPIO31 BATLOW#/GPIO72 RI#
IBEXPEAK-M-GP-NF
R567 2 1 0R0402-PAD
1 1
R576 2 0R0402-PAD R577 2 0R0402-PAD
1 1
R191 2 0R0402-PAD
TP95 TPAD14-GP
-1 1002
3D3V_S5
B
H_PM_SYNC
5
PM_RI#
1
TP64 TPAD14-GP 3D3V_S5
2
1
R533 1KR2F-3-GP
DY 10KR2J-3-GP
2
3D3V_S5 3D3V_S0 RN59 PM_CLKRUN# PCH_GPIO72 3D3V_S5 RN31 PM_RI# SUS_PW R_DN_ACK_R PM_PW RBTN#_R AC_PRESENT_R
1
R326
SB 0814
B
D28
1
39 RSMRST#_KBC
PM_RSMRST#
1
1
3
S3
8 7 6 5 2
R700 10KR2J-3-GP
DY
2
BAT54-4-GP
R535 100KR2J-1-GP
83.00054.S81 2ND = 83.00054.T81
3D3V_AUX_S5
SRN10KJ-7GP SRN8K2J-6-GP PM_SLP_S3# 3D3V_S5
S3
G
D
2
1 2
4 3
1 2 3 4
PM_SLP_S3_CTL 8,20
Q43 2N7002-11-GP
84.27002.W31 2nd = 84.27002.N31
S
EMI
1
R614 10KR2J-3-GP Q51
A
1
R657 100KR2J-1-GP
5 6
2 1
2N7002KDW -GP
2
4
3
PM_RSMRST#
51123_PGOOD
47
84.2N702.A3F 2ND = 84.DM601.03F
EC32 PM_PW ROK_1 1 2 DY SC22P50V2JN-4GP EC33 ME_PW ROK 1 2 DY SC22P50V2JN-4GP EC30 LAN_RST#1 1 2 DY SC22P50V2JN-4GP EC65 PM_RSMRST# 1 2 DY SC22P50V2JN-4GP
PCIE_W AKE#
1 R198
2 10KR2J-3-GP
-1 0925
JV70-CP
A
2
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
PCH (3/9)
Size A3 Date:
4 3 2
Document Number
Rev
JV70-CP
Thursday, October 08, 2009 Sheet
1
-1
13 of 68
5
5
4
3
2
1
PCH1D 3D3V_S0
D
4 OF 10
22 PCH_BL_ON 23 PCH_LCDVDD_ON RN22 23 L_BKLTCTL
T48 T47 Y48
CLK_DDC_EDID DAT_DDC_EDID LCTL_CLK LCTL_DATA
L_BKLTEN L_VDD_EN L_BKLTCTL L_DDC_CLK L_DDC_DATA L_CTRL_CLK L_CTRL_DATA LVD_IBG LVD_VBG LVD_VREFH LVD_VREFL LVDSA_CLK# LVDSA_CLK LVDSA_DATA#0 LVDSA_DATA#1 LVDSA_DATA#2 LVDSA_DATA#3 LVDSA_DATA0 LVDSA_DATA1 LVDSA_DATA2 LVDSA_DATA3 LVDSB_CLK# LVDSB_CLK LVDSB_DATA#0 LVDSB_DATA#1 LVDSB_DATA#2 LVDSB_DATA#3 LVDSB_DATA0 LVDSB_DATA1 LVDSB_DATA2 LVDSB_DATA3
SDVO_TVCLKINN SDVO_TVCLKINP SDVO_STALLN SDVO_STALLP SDVO_INTN SDVO_INTP
BJ46 BG46 BJ48 BG48 BF45 BH45
D
1 2
SRN10KJ-5-GP
4 3
LCTL_CLK LCTL_DATA
22 CLK_DDC_EDID 22 DAT_DDC_EDID
AB48 Y45 AB46 V48 AP39 AP41 AT43 AT42 AV53 AV51 BB47 BA52 AY48 AV47 BB48 BA50 AY49 AV48 AP48 AP47 AY53 AT49 AU52 AT53 AY51 AT48 AU50 AT51
UMA_PX
TPAD14-GP TP53
1
LIBG L_LVBG LVD_VREFH LVD_VREFL
SDVO_CTRLCLK SDVO_CTRLDATA DDPB_AUXN DDPB_AUXP DDPB_HPD DDPB_0N DDPB_0P DDPB_1N DDPB_1P DDPB_2N DDPB_2P DDPB_3N DDPB_3P DDPC_CTRLCLK DDPC_CTRLDATA DDPC_AUXN DDPC_AUXP DDPC_HPD DDPC_0N DDPC_0P DDPC_1N DDPC_1P DDPC_2N DDPC_2P DDPC_3N DDPC_3P DDPD_CTRLCLK DDPD_CTRLDATA DDPD_AUXN DDPD_AUXP DDPD_HPD DDPD_0N DDPD_0P DDPD_1N DDPD_1P DDPD_2N DDPD_2P DDPD_3N DDPD_3P
T51 T53 BG44 BJ44 AU38 BD42 PCH_HDMI_DATA2-_L BC42 PCH_HDMI_DATA2+_L BJ42 PCH_HDMI_DATA1-_L BG42 PCH_HDMI_DATA1+_L BB40 PCH_HDMI_DATA0-_L BA40 PCH_HDMI_DATA0+_L AW38PCH_HDMI_CLK-_L BA38 PCH_HDMI_CLK+_L Y49 AB49 1 C279 1 C276 1 C284 1 C280 1 C290 1 C286 1 C298 1 C296
PCH_HDMI_CLK 25 PCH_HDMI_DATA 25
R167
1
2
2K4R2F-GP
LIBG
22 PCH_TXACLK22 PCH_TXACLK+ 22 PCH_TXAOUT022 PCH_TXAOUT122 PCH_TXAOUT222 PCH_TXAOUT0+ 22 PCH_TXAOUT1+ 22 PCH_TXAOUT2+
LVDS
PCH_HDMI_DETECT
25 PCH_HDMI_DATA2- 25 PCH_HDMI_DATA2+ 25 PCH_HDMI_DATA1- 25 PCH_HDMI_DATA1+ 25 PCH_HDMI_DATA0- 25 PCH_HDMI_DATA0+ 25 PCH_HDMI_CLK- 25 PCH_HDMI_CLK+ 25
Digital Display Interface
DIS-ONLY-DY,PX->64.23715.6DL,UMA-2.4K
2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP 2 SCD1U10V2KX-5GP
UMA_PX
C
RN17
1 2
SRN0J-10-GP-U
4 3
LVD_VREFH LVD_VREFL
22 PCH_TXBCLK22 PCH_TXBCLK+ 22 PCH_TXBOUT022 PCH_TXBOUT122 PCH_TXBOUT222 PCH_TXBOUT0+ 22 PCH_TXBOUT1+ 22 PCH_TXBOUT2+
C
BE44 BD44 AV40 BE40 BD40 BF41 BH41 BD38 BC38 BB36 BA36 U50 U52 BC46 BD46 AT38 BJ40 BG40 BJ38 BG38 BF37 BH37 BE36 BD36
UMA_PX
RN50
8 7 6 5
SRN150F-1-GP
1 2 3 4
PCH_BLUE PCH_GREEN PCH_RED
22 PCH_BLUE 22 PCH_GREEN 22 PCH_RED 24 PCH_DDCCLK 24 PCH_DDCDATA 24 PCH_HSYNC 24 PCH_VSYNC
AA52 AB53 AD53 V51 V53 Y53 Y51
CRT_IREF
CRT_BLUE CRT_GREEN CRT_RED CRT_DDC_CLK CRT_DDC_DATA CRT_HSYNC CRT_VSYNC DAC_IREF CRT_IRTN
UMA_PX
B
1 2 R143 1KR2D-1-GP
AD48 AB51
CRT
B
1K 0.5% ohm
IBEXPEAK-M-GP-NF
A
JV70-CP
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
PCH (4/9)
Size A3 Date:
5 4 3 2
Document Number
Rev
JV70-CP
Thursday, October 08, 2009 Sheet
1
-1
14 of 68
5
4
3
2
1
PCH1E RN53 PCI_REQ3# PCI_REQ0# INT_PIRQB# 3D3V_S0 3D3V_S0 PCI_PERR# INT_PIRQH# PCI_TRDY# PCI_PLOCK#
5 OF 10
+V_NVRAM_VCCQ
1 2 3 4 5
10 9 8 7 6
SRN8K2J-2-GP-U
D
RN54 INT_PIRQD# PCI_FRAME# PCI_REQ1# PCI_DEVSEL# 3D3V_S0
NVRAM
1 2 3 4 5
10 9 8 7 6
SRN8K2J-2-GP-U
3D3V_S0 PCI_SERR# PCI_IRDY# PCI_STOP# INT_PIRQG#
These pins are left as NC, because the function is disable.
RN56
1 2 3 4
SRN8K2J-4-GP
8 7 6 5
INT_PIRQE# INT_PIRQF# INT_PIRQA# INT_PIRQC#
NV_ALE NV_CLE NV_RCOMP
BD3 AY6 AU2 AV7 AY8 AY5 AV11 BF5 H18 J18 A18 C18 N20 P20 J20 L20 F20 G20 A20 C20 M22 N22 B21 D21 H22 J22 E22 F22 A22 C22 G24 H24 L24 M24 A24 C24 B25 D25 N16 J16 F16 L16 E14 G16 F12 T15
NV_ALE NV_CLE NV_RCOMP 1 DY R199 32D4R2F-GP
NV_ALE
2
PCI
NV_RB# NV_WR#0_RE# NV_WR#1_RE# NV_WE#_CK0 NV_WE#_CK1 USBP0N USBP0P USBP1N USBP1P USBP2N USBP2P USBP3N USBP3P USBP4N USBP4P USBP5N USBP5P USBP6N USBP6P USBP7N USBP7P USBP8N USBP8P USBP9N USBP9P USBP10N USBP10P USBP11N USBP11P USBP12N USBP12P USBP13N USBP13P USBRBIAS#
3D3V_S0
L=> DIS H=> UMA
C
SC 0916
R153 10KR2J-3-GP INT_PIRQA# INT_PIRQB# INT_PIRQC# INT_PIRQD# PCI_REQ0# PCI_REQ1# dGPU_SELECT# PCI_REQ3# PCI_GNT0# PCI_GNT1# dGPU_PW M_SELECT# PCI_GNT3# INT_PIRQE# INT_PIRQF# INT_PIRQG# INT_PIRQH#
J50 G42 H47 G34 G38 H51 B37 A44 F51 A46 B45 M53 F48 K45 F36 H53 B41 K53 A36 A48 K6
C/BE0# C/BE1# C/BE2# C/BE3# PIRQA# PIRQB# PIRQC# PIRQD# REQ0# REQ1#/GPIO50 REQ2#/GPIO52 REQ3#/GPIO54 GNT0# GNT1#/GPIO51 GNT2#/GPIO53 GNT3#/GPIO55 PIRQE#/GPIO2 PIRQF#/GPIO3 PIRQG#/GPIO4 PIRQH#/GPIO5
USB
Pair 0
USBPN0 USBPP0 USBPN1 USBPP1 USBPN2 USBPP2 USBPN3 USBPP3 USBPN4 USBPP4 29 29 29 29 29 29 37 37 23 23
Device USB1 USB2 USB4 MINICARD1 WECAM NC NC NC NC USB3(HS) Finger Print Blue Tooth NC Cardreader
B C
2
1 2 3 4 5 6 7 8 9
22,23,24 dGPU_SELECT#
23 dGPU_PW M_SELECT#
PCI_GNT0# 1 R145 PCI_GNT1# 1 R489
DY DY
2
1KR2J-1-GP
2
1KR2J-1-GP
USE SPI
1
USB
PCIRST# SERR# PERR# IRDY# PAR DEVSEL# FRAME# PLOCK# STOP# TRDY# PME# PLTRST# CLKOUT_PCI0 CLKOUT_PCI1 CLKOUT_PCI2 CLKOUT_PCI3 CLKOUT_PCI4
IBEXPEAK-M-GP-NF
BOOT BIOS Strap PCI_GNT#0 PCI_GNT#1 BOOT BIOS Location
PCI_SERR# PCI_PERR# PCI_IRDY#
E44 E50 A42 H44 F46 C46 D49 D41 C48 M7 D5 N52 P53 P46 P51 P48
USBPN9 29 USBPP9 29 USBPN10 41 USBPP10 41 USBPN11 28 USBPP11 28 USBPN13 36 USBPP13 36 USB_RBIAS_PN
10 11 12 13
0
B
0 0 1 1
LPC(Default) Reserved PCI SPI
TP61 TPAD14-GP
1 0 1
PCI_DEVSEL# PCI_FRAME# PCI_PLOCK# PCI_STOP# PCI_TRDY#
USBRBIAS OC0#/GPIO59 OC1#/GPIO40 OC2#/GPIO41 OC3#/GPIO42 OC4#/GPIO43 OC5#/GPIO9 OC6#/GPIO10 OC7#/GPIO14
1 2 R532 22D6R2F-L1-GP
3D3V_S5 RN27 USB_OC#2 USB_OC#4 USB_OC#0 USB_OC#1
1
ICH_PME# PCI_PLTRST#
EMI
EC18 1 2 DY SC22P50V2JN-4GP EC21 CLK_PCI_FB 1 2 DY SC22P50V2JN-4GP EC31 PCI_PLTRST# 1 2 DY SC22P50V2JN-4GP PCLK_FW H 40 PCLK_FW H 12 CLK_PCI_FB 39 CLK_PCI_KBC R492 R493 R494 TPAD14-GP TPAD14-GP
1 1 1 TP48 TP50
2 22R2J-2-GP 2 22R2J-2-GP 2 47R2J-2-GP 1 1
CLK_PCI_SIO_R CLK_PCI_FB_R CLK_PCI_KBC_R CLK_PCI_3 CLK_PCI_4
USB_OC#2 USB_OC#3 USB_OC#5 USB_OC#6 USB_OC#7
USB_OC#0 29 USB_OC#1 29 USB_OC#4 29
8 7 6 5
1 2 3 4
SRN10KJ-6-GP 3D3V_S5 RN24
3D3V_S5
DY
2
U67
A
C636
1
SCD1U10V2KX-5GP
PCI_GNT3# 1 R490
DY
2 4K7R2J-2-GP
USB_OC#3 USB_OC#5 USB_OC#6 USB_OC#7
8 7 6 5
1 2 3 4
SRN10KJ-6-GP
PCI_PLTRST#
1 2 3
A VCC B DY GND Y
5 4
PLT_RST# PLT_RST# 5,30,36,37,39,40,56,58
JV70-CP
2
3D3V_S0
H40 N34 C44 A38 C36 J34 A40 D45 E36 H48 E40 C40 M48 M45 F53 M40 M43 J36 K48 F40 C42 K46 M51 J52 K51 L34 F42 J40 G46 F44 M47 H36
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31
NV_CE#0 NV_CE#1 NV_CE#2 NV_CE#3 NV_DQS0 NV_DQS1 NV_DQ0/NV_IO0 NV_DQ1/NV_IO1 NV_DQ2/NV_IO2 NV_DQ3/NV_IO3 NV_DQ4/NV_IO4 NV_DQ5/NV_IO5 NV_DQ6/NV_IO6 NV_DQ7/NV_IO7 NV_DQ8/NV_IO8 NV_DQ9/NV_IO9 NV_DQ10/NV_IO10 NV_DQ11/NV_IO11 NV_DQ12/NV_IO12 NV_DQ13/NV_IO13 NV_DQ14/NV_IO14 NV_DQ15/NV_IO15
AY9 BD1 AP15 BD8 AV9 BG8 AP7 AP6 AT6 AT9 BB1 AV6 BB3 BA4 BE4 BB6 BD6 BB7 BC8 BJ8 BJ6 BG6
NV_CLE
Set to Vss when low. Set to Vcc when high.
1
R195
DMI Termination Voltage
DY 1KR2J-1-GP
2
NV_CLE
D
If not implemented, the dual channel NAND interface signals, including NV_RCOMP, can be left as No Connect.
Danbury Technology: Disabled when Low. Enable when High.
+V_NVRAM_VCCQ
1
R194
DY 1KR2J-1-GP
A16 swap override Strap/Top-Block Swap Override jumper PCI_GNT#3 Low = A16 swap override/Top-Block Swap Override enabled High = Default
A
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
NL17SZ08DFT2G-GP
73.7SZ08.DAH 2ND = 73.01G08.L04 3RD = 73.01G08.EHG
1 R550 2 0R2J-2-GP
R549 DY 100KR2J-1-GP
1
2
PCH (5/9)
Size A3 Date: Document Number Rev
JV70-CP
Friday, October 09, 2009 Sheet
1
-1
15 of 68
5
4
3
2
5
4
3
2
1
GPIO8 has a weak[20K] internal pull up. No need to have external pull down/up. GPIO8 pin set to high at reset.
PCH1F 6 OF 10
GPIO15 has a weak[20K] internal pull down. No need to have external pull up/down. GPIO 15 pin is set to low at reset. Low : ME Crypto TLS with no confidentiality High : ME Crypto TLS with confidentiality
D
PCH_GPIO0 EC_SMI# PX_HDMI# 39 39 EC_SCI# EC_SW I# EC_SCI# EC_SW I# PCH_GPIO12 PCH_GPIO15
Y3 C38 D37 J32 F10 K9 T7 AA2 F38 Y7 H10 AB12 V13 M11 V6 AB7 AB13 V3 P3 H3 F1 AB6 AA4 F8 B4 B52 BH2 BH52 D2 A4 A49 A5 A50 A52 A53 B2 B53 BE1 BE53 BF1 BF53 BH1 BH53 BJ1 BJ2 BJ4 BJ49 BJ5 BJ50 BJ52 BJ53 D1 D53 E1 E53
BMBUSY#/GPIO0 TACH1/GPIO1 TACH2/GPIO6 TACH3/GPIO7 GPIO8 LAN_PHY_PWR_CTRL/GPIO12 GPIO15 SATA4GP/GPIO16 TACH0/GPIO17
CLKOUT_PCIE6N CLKOUT_PCIE6P
AH45 AH46
GPIO27 has a weak[20K] internal pull up. To enable on-die PLL Voltage regurator, should not place external pull down.
MISC
CLKOUT_PCIE7N CLKOUT_PCIE7P
AF48 AF47
D
A20GATE
U2
KA20GATE 39
3D3V_S5 RN64 PCH_GPIO28 PCH_GPIO12 EC_SW I#
58 DGPU_HOLD_RST# 53,57,58 DGPU_PW ROK
DGPU_HOLD_RST# DGPU_PW ROK PCH_GPIO22
CLKOUT_BCLK0_N/CLKOUT_PCIE8N CLKOUT_BCLK0_P/CLKOUT_PCIE8P
AM3 AM1 BG10 T1 BE10 BD10
BCLK_CPU_N_R BCLK_CPU_P_R
1 1
R735 2 0R0402-PAD R736 2 0R0402-PAD
BCLK_CPU_N 5 BCLK_CPU_P 5
TPAD14-GP TPAD14-GP
TP57 TP63
1 1
PCH_GPIO24 PCH_GPIO27 PCH_GPIO28
GPIO
5 6 7 8
4 3 2 1
SCLOCK/GPIO22 GPIO24 GPIO27 GPIO28 STP_PCI#/GPIO34
PECI RCIN#
H_PECI 5 KBRCIN# 39 1D05V_VTT
CPU
SB 0813
SRN10KJ-7GP
PROCPWRGD THRMTRIP#
H_PW RGD 5,43,56
1 2 R196 56R2J-4-GP
PM_THRMTRIP-A# 5,43
PCH_GPIO45
R714 1 2 8K2R2J-3-GP R226 1 2 1KR2J-1-GP 57 DGPU_PW R_EN#
STP_PCI# PCH_GPIO35 DGPU_PW R_EN# dGPU_PRSNT# 22,24 dGPU_EDID 11 PCH_GPIO39 dGPU_EDID PCH_GPIO39 PCH_GPIO45
PCH_THERMTRIP_R
SB 0814
PCH_GPIO15
C
SATACLKREQ#/GPIO35 SATA2GP/GPIO36 SATA3GP/GPIO37 SLOAD/GPIO38 SDATAOUT0/GPIO39 PCIECLKRQ6#/GPIO45 PCIECLKRQ7#/GPIO46 SDATAOUT1/GPIO48 SATA5GP/GPIO49 GPIO57 VSS_NCTF_8 VSS_NCTF_9 VSS_NCTF_16 VSS_NCTF_17 VSS_NCTF_28 VSS_NCTF#A4 VSS_NCTF#A49 VSS_NCTF#A5 VSS_NCTF#A50 VSS_NCTF#A52 VSS_NCTF#A53 VSS_NCTF#B2 VSS_NCTF#B53 VSS_NCTF#BE1 VSS_NCTF#BE53 VSS_NCTF#BF1 VSS_NCTF#BF53 VSS_NCTF#BH1 VSS_NCTF#BH53 VSS_NCTF#BJ1 VSS_NCTF#BJ2 VSS_NCTF#BJ4 VSS_NCTF#BJ49 VSS_NCTF#BJ5 VSS_NCTF#BJ50 VSS_NCTF#BJ52 VSS_NCTF#BJ53 VSS_NCTF#D1 VSS_NCTF#D53 VSS_NCTF#E1 VSS_NCTF#E53 TP1 TP2 TP3 TP4 TP5 TP6 TP7 TP8 TP9 TP10 TP11 BA22
1 DY 2 R197 54D9R2F-L1-GP
Placed Within 2" from
AW22 BB22 AY45
1D5V_S3
PCH
C
AY46 AV43 AV45 1
R23 1KR2F-3-GP
SB 0814
20,21 RST_GATE
RST_GATE PCH_GPIO48
11
PSW _CLR#
2
PSW _CLR# UMA_DISCRETE#
SB 0819
AF13 M18 N18 AJ24 AK41 AK42
RST_GATE 3D3V_S5
S3
SB 0813
DDR3_DRAMRST#
20,21
NCTF
RSVD
H: No SG function L: SG Support
3D3V_S0
H: DIS ONLY L: SG and UMA
3D3V_S5 TP94 AFTE14P-GP
TP13
C
2
1
NCTF_28
TP12
S3
B
Q47 MMBT3904-4-GP
1
R710 10KR2F-2-GP
1
SB 0813
S3
SB 0819
NON-S3
R709 0R2J-2-GP
2
2
UMA_DIS-ONLY
R185 10KR2J-3-GP
UMA_PX
R699 10KR2J-3-GP
NCTF TEST PIN: A4,A49,A5,A50,A52,A53,B2,B53,BE1, BE53,BF1,BF53,BH1,BH53,BJ1,BJ2,BJ4, BJ49,BJ5,BJ50,BJ52,BJ53,D1,D53,E1,E53
TP14 TP15 TP16 TP17 TP18 TP19 NC_1 NC_2 NC_3 NC_4 NC_5 INIT3_3V# TP24
N32 M30 N30 H12 AA23 AB45 AB38 AB42 AB41 T39 P6 C10
INIT3_3V# C890 SCD047U25V2KX-GP
TP89 AFTE14P-GP
1
NCTF#A53
1
S3
B
1
B
2
2
2
dGPU_PRSNT# R187 10KR2J-3-GP
1
UMA_DISCRETE# R698 10KR2J-3-GP
E
SB 0819
84.T3904.C11 2ND = 84.03904.L06
SM_DRAMRST# 5
1
PX
1 1
DIS-ONLY
TP93 AFTE14P-GP
S3
2
R34 100KR2F-L1-GP
1
NCTF#BJ2
TP88 AFTE14P-GP
1
NCTF#BJ53
2
M32
SB 0814
1
TP62 TPAD14-GP
3D3V_S0 RN67
IBEXPEAK-M-GP-NF
11,39 INT_SERIRQ 11 SATA_DET#0_R
5 PCH_GPIO48 6 INT_SERIRQ 7 SATA_DET#0_R8
4 3 2 1
SRN10KJ-7GP
A
RN30 STP_PCI# dGPU_EDID PCH_GPIO0 PCH_GPIO22 3D3V_S0
PSW _CLR#
EMI
EC68 DGPU_HOLD_RST# 1 2 DY SC22P50V2JN-4GP EC23 DGPU_PW ROK 1 2 DY SC22P50V2JN-4GP
JV70-CP
A
1
1 2 3 4 5
SRN10KJ-L3-GP
10 9 8 7 6
EC_SCI# EC_SMI# PX_HDMI#
2
RP1
3D3V_S0
PCH_GPIO35 DGPU_HOLD_RST# DGPU_PW R_EN#
5 6 7 8
4 3 2 1
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
GAP-OPEN
G111
SRN10KJ-7GP
PCH (6/9)
Size A3 Date: Document Number Rev
JV70-CP
Thursday, October 08, 2009 Sheet
1
-1
16 of 68
5
4
3
2
5
4
3
2
1
1D05V_S0
1.432A
1 1
C329 SC10U6D3V3MX-GP C332 SC1U6D3V2KX-GP
PCH1G
POWER
CRT
7 OF 10
2
2
2
2
VSSA_DAC VSSA_DAC
VCC CORE
2
AF51
3D3V_S0
2
D
AB24 AB26 AB28 AD26 AD28 AF26 AF28 AF30 AF31 AH26 AH28 AH30 AH31 AJ30 AJ31
VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE VCCCORE
VCCADAC VCCADAC
AE50 AE52 AF53
+VCCA_DAC_1_2
1
1
1
R142 DY 0R2J-2-GP
C265 SCD01U50V2KX-1GP
C258 SCD1U10V2KX-5GP
1
1 R485 2 0R0603-PAD
SC10U6D3V3MX-GP
69mA
3D3V_S0_DAC
C595
D
DY
+3VS_VCCA_LVD
VCCALVDS VSSA_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS VCCTX_LVDS
AH38 AH39 AP43 AP45 AT46 AT45
1 R157 2 0R3J-0-U-GP
300mA
1D8V_S0
For LVDS function Disable , Can be connected to GND directly
UMA_PX
+1.8VS_VCCTX_LVDS 1 R527 2 C619 0R3J-0-U-GP SCD01U16V2KX-3GP SCD01U16V2KX-3GP
1D05V_S0
59mA
+3VS_VCCA_LVD +1.8VS_VCCTX_LVDS
DIS-ONLY
1 R166 2
1
1
LVDS
C285
C281
1
2
2
42mA
1 DY 2 L25 IND-1UH-2-GP
+1.05VS_VCCAPLL_EXP
2
1D05V_S0
AK24 BJ24 AN20 AN22 AN23 AN24 AN26 AN28 BJ26 BJ28 AT26 AT28 AU26 AU28 AV26 AV28 AW26 AW28 BA26 BA28 BB26 BB28 BC26 BC28 BD26 BD28 BE26 BE28 BG26 BG28 BH27 AN30 AN31
VCCIO VCCAPLLEXP
DY
UMA_PX
UMA_PX UMA_PX
UMA_PX
SC10U6D3V3MX-GP
0R3J-0-U-GP
1 R517
2
C623 SC10U6D3V3MX-GP
VCC3_3 VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCC3_3 VCCVRM[1] VCCFDIPLL VCC3_3
1
AB34 AB35 AD35
0R3J-0-U-GP
DY
2
HVCMOS
VCC3_3
357mA
1
C357 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
3D3V_S0
DIS-ONLY
1D05V_S0
C
-1 0929
1 1 1 1 1
C328 SC10U6D3V3MX-GP C314 SC10U6D3V3MX-GP SC10U6D3V3MX-GP C326 SC1U6D3V2KX-GP C322 SC1U6D3V2KX-GP C305 SC1U6D3V2KX-GP
1
1
TC23 ST330U2VBM-GP
3.062A
DY
2 2
2
C
C331 SC1U6D3V2KX-GP SC1U6D3V2KX-GP
DY
2
DY
2
2
2
77.23371.27L 2ND = 80.3371V.12L
2
1D5V_S0_1D8V_S0
VCCVRM
AT24 AT16 AU16 1
196mA
+1.1VS_VCC_DMI
VCCDMI: 1.05V: 58mA 1.1V: 61mA
1D05V_VTT
DMI
VCCDMI VCCDMI
2
PCI E*
2
SC1U6D3V2KX-GP
1 DY 2 R540 0R3J-0-U-GP
+V_NVRAM_VCCQ
1
R210 0R0603-PAD
1
R208
3D3V_S0
1 R538 2 0R0603-PAD
C345
61mA
1D05V_S0
1D8V_S0
3D3V_S0
DY 0R3J-0-U-GP
1 2
C300 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
1 DY 2 L27 IND-1UH-2-GP
B
1
C624 SC10U6D3V3MX-GP
DY
2
1D05V_S0
357mA
VCCAFDI_VRM +1.05VS_VCCAPLL_FDI
AN35 AT22 BJ18 AM23
NAND / SPI
2
1D05V_S0
VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND VCCPNAND
AM16 AK16 AK20 AK19 AK15 AK13 AM12 AM13 AM15
156mA
1
C347 SCD1U10V2KX-5GP
2
VCCPNAND which power the DC NAND interface must be powered even if dual channel NAND interface is not connected since it also supplies power to other functions inside PCH.
B
FDI
VCCIO
VCCME3_3 VCCME3_3 VCCME3_3 VCCME3_3
AM8 AM9 AP11 AP9
3D3V_S0
85mA
1 2
VCCME3_3
1
1
1
1
C330 SC1U6D3V2KX-GP
C338 SC1U6D3V2KX-GP
C316 SC1U6D3V2KX-GP
C320 C311 SC10U6D3V3MX-GP SC1U6D3V2KX-GP
1
1 R193 2 0R0603-PAD
5V_S0
DY
2
C350 SCD1U10V2KX-5GP
2
2
2
2
IBEXPEAK-M-GP-NF
Imax = 300 mA
U57
3D3V_S0_DAC
1 NC#4 4
BC6 SC1U16V3ZY-GP
-1 0929
1 2 3
SC1U16V3ZY-GP
VIN GND EN
VOUT
5
C590 SC22U6D3V5MX-2GP
1
G9091-330T11U-GP BC5
2
VCCAFDI_VRM
1 R175 2 0R0603-PAD
1D5V_S0_1D8V_S0
A
-1 0929
JV70-CP
A
1D8V_S0
1D5V_S0
1 R173 2 0R0603-PAD
Wistron Corporation
21F, 88, Sec.1, Hsin Tai W u Rd., Hsichih, Taipei Hsien 221, Taiwan, R.O.C. Title
1
R172
DY
2 0R3J-0-U-GP
PCH (7/9)
Size A3 Date:
5 4 3 2
Document Number
2
1D5V_S0_1D8V_S0
74.09091.J3F
1
DY
2
Rev
JV70-CP
Thursday, October 08, 2009 Sheet
1
-1
17 of 68
5
4
3
2
1
1D05V_S0
52mA
-1 1002
1D05V_S0 R176 1
D
L9
+1.05VS_VCCA_CLK SC10U6D3V3MX-GP SC1U10V2KX-1GP
1
DY
2
PCH1J
POWER
10 OF 10
1D05V_S0
1
IND-10UH-215-GP
C310
1
C272
AP51 AP53 AF23
1
68.1001D.10E
DY
2
DY
2
VCCACLK VCCACLK VCCLAN VCCLAN DCPSUSBYP VCCME VCCME VCCME VCCME VCCME VCCME
VCCIO VCCIO VCCIO VCCIO VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCSUS3_3 VCCIO V5REF_SUS
V24 V26 Y24 Y26 V28 U28 U26 U24 P28 P26 N28 N26 M28 M26 L28 L26 J28 J26 H28 H26 G28 G26 F28 F26 E28 E26 C28 C26 B27 A28 A26 U23 V23 F24
C304 SC1U6D3V2KX-GP 3D3V_S5
2 0R2J-2-GP
+1.05VS_VCCLAN
AF24
DCPSUSBYP
DY
VccLAN may be grounded if Intel LAN is disabled
R177 0R0402-PAD
2
2
D
1
1
1
C333 SC1U6D3V2KX-GP
Y20 AD38
C319 SC1U6D3V2KX-GP
1 2
C325 SC1U6D3V2KX-GP
DY
2
C336 SCD1U10V2KX-5GP
1
C327 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
2
1
2
USB
AD39 AD41 AF43 1 AF41
C321
2
1D05V_S0
-1 0929
3D3V_S5
1.849A
1
C313
1
C324 SC10U6D3V3MX-GP
1 2
C317 SCD1U10V2KX-5GP 3D3V_S5
AF42 V39 V41 V42 Y39 Y41 Y42
SC1U6D3V2KX-GP
2
2
2
SC10U6D3V3MX-GP
VCCME VCCME VCCME VCCME VCCME
Clock and Miscellaneous
VCCME
2
3D3V_S0 D27 CH751H-40PT-GP
1
2
1
C
68.1001D.10E
SC10U6D3V3MX-GP
C604
1
1 2 IND-10UH-215-GP
+1.05VS_VCCA_A_DPL C602 SC1U6D3V2KX-GP
5V_S5 +5VALW _PCH_VCC5REFSUS
2
D26 CH751H-40PT-GP
1D05V_S0
L22
C315 SC1U10V2KX-1GP
1
-1 1002
DY
1D05V_S0
83.R0304.A8F 2ND = 83.R2004.C8F
2
2
+VCCRTCEXT
1
DY
1mA
-1 0925
2
V9
DCPRTC
1
1D5V_S0_1D8V_S0
C620 SC1U10V2KX-1GP
1
1 R529
2 10R2J-2-GP
83.R0304.A8F 2ND = 83.R2004.C8F
5V_S0
C
L23
2
PCI/GPIO/LPC
1
68.1001D.10E
SC10U6D3V3MX-GP
DY
2 2
VCCADPLLA VCCADPLLA VCCADPLLB VCCADPLLB VCCIO VCCIO VCCIO VCCIO
VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3 VCC3_3
L38 M36 1 N36 P36 U35 AD13
C370 SCD1U10V2KX-5GP SCD1U10V2KX-5GP
3D3V_S0
BD51 BD53 AH23 AJ35 AH35 AF34
1D05V_S0
2
3D3V_S0 SCD1U10V2KX-5GP C362 1
2
1
1
1
AH34 AF32
C306 SC1U6D3V2KX-GP
C635 SC1U6D3V2KX-GP
C335 SC1U6D3V2KX-GP
VCCIO VCCIO DCPSST VCCSATAPLL VCCSATAPLL AK3 AK1
+1.05VS_VCCAPLL
L10
1D05V_S0
2
2
2
1 1
C633 SC1U10V2KX-1GP DY
1
V12
B
DY
2
32mA
-1 1002
1D05V_S0
B
C634
IND-10UH-215-GP
+VCCSST
DY SC1U10V2KX-1GP
2
68.1001D.10E
1
+1.1VALW _INT_VCCSUS
Y22
2
2
C323 SCD1U10V2KX-5GP
1D5V_S0_1D8V_S0
1
C344 SCD1U10V2KX-5GP
DCPSUS VCCIO
1
AH22
C334 SC1U6D3V2KX-GP
2
P18 U19
VCCSUS3_3
VCCVRM
AT20 AH19 AD20 AF22 AD19 AF20 AF19 AH20 AB19 AB20 AB22 AD22 AA34 Y34 Y35 AA35 L30 1
C618 SC1U6D3V2KX-GP PCH_VCC_1_1_20 PCH_VCC_1_1_21 PCH_VCC_1_1_22 PCH_VCC_1_1_23
DY
2
163mA
1 2
C318 SCD1U10V2KX-5GP 3D3V_S0
PCI/GPIO/LPC
VCCSUS3_3 VCCSUS3_3 VCCSUS3_3
SATA
3D3V_S5
U20 U22
VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCIO VCCME VCCME VCCME VCCME VCCSUSHDA
-1 0929
V15 1 V16 2
C368 SCD1U10V2KX-5GP
VCC3_3 VCC3_3 VCC3_3
+3VS_+1.5VS_HDA_IO
1 R525 2 0R0603-PAD
2
C605
1
1 2 IND-10UH-215-GP
+1.05VS_VCCA_B_DPL C603 SC1U6D3V2KX-GP
1
C348 SC