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AT90S1200
Features
ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ ˇ
Utilizes the AVR Ž Enhanced RISC Architecture AVR - High Performance and Low Power RISC Architecture 89 Powerful Instructions - Most Single Clock Cycle Execution 1K bytes of In-System Reprogrammable Downloadable Flash - SPI Serial Interface for Program Downloading - Endurance: 1,000 Write/Erase Cycles 64 bytes EEPROM - Endurance: 100,000 Write/Erase Cycles 32 x 8 General Purpose Working Registers 15 Programmable I/O Lines VCC: 2.7 - 6.0V Fully Static Operation, 0 - 16 MHz Instruction Cycle Time: 62.5 ns @ 16 MHz One 8-Bit Timer/Counter with Separate Prescaler External and Internal Interrupt Sources Programmable Watchdog Timer with On-Chip Oscillator On-Chip Analog Comparator Low Power Idle and Power Down Modes Programming Lock for Software Security 20-Pin Device Selectable On-Chip RC Oscillator for Zero External Components

8-Bit Microcontroller with 1K bytes Downloadable Flash AT90S1200

Description
The AT90S1200 is a low-power CMOS 8-bit microcontroller based on the AVR Ž enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S1200 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. The AVR core combines a rich instruction set with the 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers.

(continued)

Pin Configuration

0838A

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Block Diagram

Figure 1. The AT90S1200 Block Diagram

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AT90S1200

AT90S1200
Description (Continued)
The architecture supports high level languages efficiently as well as extremely dense assembler code programs. The AT90S1200 provides the following features: 1K bytes of Downloadable Flash, 64 bytes EEPROM, 15 general purpose I/O lines, 32 general purpose working registers, internal and external interrupts, programmable Watchdog Timer with internal oscillator, an SPI serial port for program downloading and two software selectable power saving modes. The Idle Mode stops the CPU while allowing the registers, timer/counter, watchdog and interrupt system to continue functioning. The power down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next external interrupt or hardware reset. The device is manufactured using Atmel's high density non-volatile memory technology. The on-chip Downloadable Flash allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an enhanced RISC 8-bit CPU with Downloadable Flash on a monolithic chip, the Atmel AT90S1200 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90S1200 AVR is supported with a full suite of program and system development tools including: macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits.

Pin Descriptions
VCC Supply voltage pin. GND Ground pin. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O port. Port pins can provide internal pullups (selected for each bit). PB0 and PB1 also serve as the positive input (AIN0) and the negative input (AIN1), respectively, of the on-chip analog comparator. The Port B output buffers can sink 20mA and can drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current (IIL) if the internal pullups are activated. Port B also serves the functions of various special features of the AT90S1200 as listed on Page 2-27. Port D (PD6..PD0) Port D has seven bi-directional I/O pins with internal pullups, PD6..PD0. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current (IIL) if the pullups are activated. Port D also serves the functions of various special features of the AT90S1200 as listed on Page 2-31. RESET Reset input. A low on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier

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Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an onchip oscillator, as shown in Figure 2. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 3.

Figure 2. Oscillator Connections

Figure 3. External Clock Drive Configuration

On-Chip RC Oscillator
An on-chip RC oscillator running at a fixed frequency of 1 MHz can be selected as the MCU clock source. If enabled, the AT90S1200 can operate with no external components. A control bit - RCEN in the Flash Memory selects the on-chip RC oscillator as the clock source when programmed (`0'). The AT90S1200 is normally shipped with this bit unprogrammed (`1'). Parts with this bit programmed can be ordered as AT90S1200A. The RCEN-bit can be changed by parallel programming only. When using the on-chip RC oscillator for serial program downloading, the RCEN bit must programmed in parallel programming mode first.

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AT90S1200

AT90S1200
AT90S1200 AVR Enhanced RISC Microcontroller CPU
The AT90S1200 AVR RISC microcontroller is upward compatible with the AVR Enhanced RISC Architecture. The programs written for the AT90S1200 MCU are compatible with the range of AVR 8-bit MCUs (AT90Sxxxx) with respect to source code and clock cycles for execution.

Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file - in one clock cycle.

Figure 4. The AT90S1200 AVR Enhanced RISC Architecture The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 4 shows the AT90S1200 AVR Enhanced RISC microcontroller architecture. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data memories. The program memory is accessed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory. With the relative jump and relative call instructions, the whole 512 address space is directly accessed. All AVR instructions have a single 16-bit word format, meaning that every program memory address contains a single 16-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is a 3 level deep hardware stack dedicated for subroutines and interrupts. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/Dconverters, and other I/O functions. The memory spaces in the AVR architecture are all linear and regular memory maps.

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A flexible interrupt module has its control registers in the I/O space with an additional global interrupt enable bit in the status register. All the different interrupts have a separate interrupt vector in the interrupt vector table at the beginning of the program memory. The different interrupts have priority in accordance with their interrupt vector position. The lower the interrupt address vector the higher priority.

The General Purpose Register File
Figure 5 shows the structure of the 32 general purpose registers in the CPU.
7 R0 R1 R2 General Purpose Working Registers ... ... R28 R29 R30 (Z-Register) R31 0

Figure 5. AVR CPU General Purpose Working Registers All the register operating instructions in the instruction set have direct and single cycle access to all registers. The only exception is the five constant arithmetic and logic instructions SBCI, SUBI, CPI, ANDI, ORI between a constant and a register and the LDI instruction for load immediate constant data. These instructions apply to the second half of the registers in the register file - R16..R31. The general SBC, SUB, CP, AND, OR and all other operations between two registers or on a single register apply to the entire register file. Register 30 also serves as an 8-bit pointer for indirect address of the register file.

The ALU - Arithmetic Logic Unit
The high-performance AVR ALU operates in direct connection with all the 32 general purpose working registers. Within a single clock cycle, ALU operations between registers in the register file are executed. The ALU operations are divided into three main categories - arithmetic, logic and bit-functions. Some microcontrollers in the AVR product family feature a hardware multiplier in the arithmetic part of the ALU.

The Downloadable Flash Program Memory
The AT90S1200 contains 1K bytes on-chip downloadable Flash memory for program storage. Since all instructions are single 16-bit words, the Flash is organized as 512 x 16 words. The Flash memory has an endurance of at least 1000 write/ erase cycles. The AT90S1200 Program Counter is 9-bit wide, thus addressing the 512 words Flash program memory. See Page 2-34 for a detailed description on Flash data downloading.

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AT90S1200

AT90S1200
The Program and Data Addressing Modes
The AT90S1200 AVR Enhanced RISC Microcontroller supports powerful and efficient addressing modes. This section describes the different addressing modes supported in the AT90S1200. In the figures, OP means the operation code part of the instruction word. To simplify, not all figures show the exact location of the addressing bits. REGISTER DIRECT, SINGLE REGISTER RD

Figure 6. Direct Single Register Addressing The operand is contained in register d (Rd). REGISTER INDIRECT

Figure 7. Indirect Register Addressing The register accessed is the one pointed to by the Z-register (R30).

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REGISTER DIRECT, TWO REGISTERS RD AND RR

Figure 8. Direct Register Addressing, Two Registers Operands are contained in register r (Rr) and d (Rd). The result is stored in register d (Rd). I/O DIRECT

Figure 9. I/O Direct Addressing Operand address is contained in 6 bits of the instruction word. n is the destination or source register address. RELATIVE PROGRAM ADDRESSING, RJMP AND RCALL

Figure 10. Relative Program Memory Addressing Program execution continues at address PC + k. The relative address k is in the range from -2K to +(2K - 1).

Subroutine and Interrupt Hardware Stack
The AT90S1200 uses a 3 level deep hardware stack for subroutines and interrupts. The hardware stack is 9 bit wide and stores the Program Counter - PC - return address while subroutines and interrupts are executed. RCALL instructions and interrupts push the PC return address onto stack level 0, and the data in the other stack levels 1-2 are pushed one level deeper in the stack. When a RET or RETI instruction is executed the returning PC is fetched from the stack level 0, and the data in the other stack levels 1-2 are popped one level in the stack. If more than 3 subsequent subroutine calls or interrupts are executed, the first values written to the stack are overwritten.

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AT90S1200

AT90S1200
The EEPROM Data Memory
The AT90S1200 contains 64 bytes of data EEPROM memory. It is organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described on Page 2-24 specifying the EEPROM address register, the EEPROM data register, and the EEPROM control register. For the SPI data downloading, see Page 2-40 for a detailed description.

Instruction Execution Timing
This section describes the general access timing concepts for instruction execution and internal memory access. The AVR CPU is driven by the System Clock Ř, directly generated from the external clock crystal for the chip. No internal clock division is used. Figure 11 shows the parallel instruction fetches and instruction executions enabled by the Harvard architecture and the fast-access register file concept. This is the basic pipelining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost, functions per clocks, and functions per power-unit.
T1 T2 T3 T4

System Clock Ř

1'st Instruction Fetch 1'st Instruction Execute 2'nd Instruction Fetch 2'nd Instruction Execute 3'rd Instruction Fetch 3'rd Instruction Execute 4'th Instruction Fetch

Figure 11. The Parallel Instruction Fetches and Instruction Executions Figure 12 shows the internal timing concept for the register file. In a single clock cycle an ALU operation using two register operands is executed, and the result is stored back to the destination register.
T1 T2 T3 T4

System Clock Ř

Total Execution Time Register Operands Fetch ALU Operation Execute Store Result in Register

Figure 12. Single Cycle ALU Operation

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I/O Memory
The I/O space definition of the AT90S1200 is shown in the following table:
Table 1. The AT90S1200 I/O Space
Address Hex $3F $3B $39 $38 $35 $33 $32 $21 $1E $1D $1C $18 $17 $16 $12 $11 $10 $08 Name SREG GIMSK TIMSK TIFR MCUCR TCCR0 TCNT0 WDTCR EEAR EEDR EECR PORTB DDRB PINB PORTD DDRD PIND ACSR Function Status REGister General Interrupt MaSK register Timer/Counter Interrupt MaSK register Timer/Counter Interrupt Flag register MCU general Control Register Timer/Counter 0 Control Register Timer/Counter 0 (8-bit) Watchdog Timer Control Register EEPROM Address Register EEPROM Data Register EEPROM Control Register Data Register, Port B Data Direction Register, Port B Input Pins, Port B Data Register, Port D Data Direction Register, Port D Input Pins, Port D Analog Comparator Control and Status Register

Note: Reserved and unused locations are not shown in the table. All the different AT90S1200 I/Os and peripherals are placed in the I/O space. The different I/O locations are accessed by the IN and OUT instructions transferring data between the 32 general purpose working registers and the I/O space. I/O registers within the address range $00 - $1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the instruction set chapter for more details. The different I/O and peripherals control registers are explained in the following sections. THE STATUS REGISTER - SREG The AVR status register - SREG - at I/O space location $3F is defined as:
Bit $3F Read/Write Initial value 7 I R/W 0 6 T R/W 0 5 H R/W 0 4 S R/W 0 3 V R/W 0 2 N R/W 0 1 Z R/W 0 0 C R/W 0 SREG

Bit 7 - I : Global Interrupt Enable:

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual interrupt enable control is then performed in the interrupt mask registers - GIMSK/TIMSK. If the global interrupt enable register is cleared (zero), none of the interrupts are enabled, independent of the GIMSK/TIMSK values. The I-bit is cleared by hardware after an interrupt has occurred, and is set by the RETI instruction to enable subsequent interrupts.

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AT90S1200

AT90S1200
Bit 6 - T : Bit Copy Storage:

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T bit as source and destination for the operated bit. A bit from a register in the register file can be copied into T by the BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD instruction.
Bit 5 - H : Half Carry Flag:

The half carry flag H indicates a half carry in some arithmetic operations. See the Instruction Set Description for detailed information.
Bit 4 - S : Sign Bit, S = NV :

The S-bit is always an exclusive or between the negative flag N and the two's complement overflow flag V. See the Instruction Set Description for detailed information.
Bit 3 - V : Two's Complement Overflow Flag:

The two's complement overflow flag V supports two's complement arithmetics. See the Instruction Set Description for detailed information.
Bit 2 - N : Negative Flag:

The negative flag N indicates a negative result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.
Bit 1 - Z : Zero Flag:

The zero flag Z indicates a zero result after the different arithmetic and logic operations. See the Instruction Set Description for detailed information.
Bit 0 - C : Carry Flag:

The carry flag C indicates a carry in an arithmetic or logic operation. See the Instruction Set Description for detailed information.

Reset and Interrupt Handling
The AT90S1200 provides 3 different interrupt sources. These interrupts and the separate reset vector, each have a separate program vector in the program memory space. All the interrupts are assigned individual enable bits which must be set (one) together with the I-bit in the status register in order to enable the interrupt. The lowest addresses in the program memory space are automatically defined as the Reset and Interrupt vectors. The complete list of vectors is shown in Table 2. The list also determines the priority levels of the different interrupts. The lower the address the higher is the priority level. RESET has the highest priority, and next is INT0 - the External Interrupt Request 0 etc.
Table 2. Reset and Interrupt Vectors
Vector No. 1 2 4 5 Program Address $000 $001 $002 $003 Source RESET INT0 TIMER0, OVF0 ANA_COMP Interrupt Definition Hardware Pin and Watchdog Reset External Interrupt Request 0 Timer/Counter0 Overflow Analog Comparator

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The most typical and general program setup for the Reset and Interrupt Vector Addresses are:
Address $000 $001 $002 $003 ; $004 ... MAIN: ... ... xxx ... ; Main program start Labels Code rjmp rjmp rjmp rjmp RESET EXT_INT0 TIM0_OVF ANA_COMP Comments ; Reset handle ; IRQ0 handle ; Timer0 overflow handle ; Analog Comparator Handle

RESET SOURCES The AT90S1200 has three sources of reset: ˇ Power-On Reset. The MCU is reset when a supply voltage is applied to the V CC and GND pins. ˇ External Reset. The MCU is reset when a low level is present on the RESET pin for more than two XTAL cycles ˇ Watchdog Reset. The MCU is reset when the Watchdog timer period expires and the Watchdog is enabled. During reset, all I/O registers are then set to their initial values, and the program starts execution from address $000. The instruction placed in address $000 must be an RJMP - relative jump - instruction to the reset handling routine. If the program never enables an interrupt source, the interrupt vectors are not used, and regular program code can be placed at these locations. The circuit diagram in Figure 13 shows the reset logic. Table 3 defines the timing and electrical parameters of the reset circuitry. Note that Power On Reset timing is clocked by the internal RC oscillator. Refer to characterization datdata for RC oscillator frequency at other VCC voltages.

Figure 13. Reset Logic
Table 3. Reset Characteristics (VCC = 5.0V)
Symbol VPOT VRST tPOR tTOUT Parameter Power-On Reset Threshold Voltage Pin Threshold Voltage Power-On Reset Period Reset Delay Time-Out Period 2 11 Min 1.8 Typ 2 VCC/2 3 16 4 21 Max 2.2 Units V V ms ms

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AT90S1200

AT90S1200
POWER-ON RESET A Power-On Reset (POR) circuit ensures that the device is not started until VCC has reached a safe level. As shown in Figure 13, an internal timer clocked from the Watchdog timer oscillator prevents the MCU from starting until after a certain period after VCC has reached the Power-On Threshold voltage - VPOT, regardless of the VCC rise time (see Figure 14 and Figure 15). The total reset period is the Power-On Reset period - tPOR + the Delay Time-out period - tTOUT.

Figure 14. MCU Start-Up, RESET Tied to VCC or Unconnected. Rapidly Rising VCC.

Figure 15. MCU Start-Up, RESET Tied to VCC or Unconnected. Slowly Rising VCC

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As the RESET pin is pulled high by an on-chip resistor, the pin can be left unconnected if no external reset is required. Connecting RESET to VCC will have the same effect. By holding the RESET pin low for a period after VCC has been applied, the Power-On Reset period can be extended. Refer to Figure 16 for a timing example on this.

Figure 16. MCU Start-Up, RESET Controlled Externally EXTERNAL RESET An external reset is generated by a low level on the pin. The pin must be held low for at least two crystal clock cycles. When reaches the Reset Threshold Voltage - VRST on its positive edge, the delay timer starts the MCU after the Time-out period tTOUT has expired.

Figure 17. External Reset During Operation

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AT90S1200

AT90S1200
WATCHDOG RESET When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT. Refer to Page 2-23 for details on operation of the Watchdog.

Figure 18. Watchdog Reset During Operation INTERRUPT HANDLING The AT90S1200 has two Interrupt Mask control registers GIMSK - General Interrupt MASK register - at I/O space address $3B and the TIMSK - Timer/Counter Interrupt MaSK register at I/O address $39. When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all interrupts are disabled. The user software can set (one) the I-bit to enable interrupts. The I-bit is set (one) when a Return from Interrupt instruction - RETI - is executed. When the Program Counter is vectored to the actual interrupt vector in order to execute the interrupt handling routine, hardware clears the corresponding flag that generated the interrupt. Some of the interrupt flags can also be cleared by writing a logic one to the flag bit position(s) to be cleared. THE GENERAL INTERRUPT MASK REGISTER - GIMSK
Bit $3B Read/Write Initial value 7 R 0 6 INT0 R/W 0 5 R 0 4 R 0 3 R 0 2 R 0 1 R 0 0 R 0 GIMSK

Bit 7 - Res : Reserved bit:

This bit is a reserved bit in the AT90S1200 and always read zero.
Bit 6 - INT0 : External Interrupt Request 0 Enable:

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the external pin interrupt is activated. The Interrupt Sense Control0 bit 1/0 (ISC01 and ISC00) in the MCU general Control Register (MCUCR) defines whether the external interrupt is activated on rising or falling edge of the INT0 pin or level sensed. INT0 can activated even if the pin is configured as an output. See also Page 2-18.
Bits 5..0 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read as zero.

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THE TIMER/COUNTER INTERRUPT MASK REGISTER - TIMSK
Bit $39 Read/Write Initial value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 TOIE0 R/W 0 0 R 0 TIMSK

Bits 7..2 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.
Bit 1 - TOIE0 : Timer/Counter0 Overflow Interrupt Enable:

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt (at vector $002) is executed if an overflow in Timer/Counter0 occurs. The Overflow Flag (Timer0) is set (one) in the Timer/Counter Interrupt Flag Register - TIFR.
Bit 0 - Res: Reserved bit:

This bits is a reserved bit in the AT90S1200 and always reads zero. THE TIMER/COUNTER INTERRUPT FLAG REGISTER - TIFR
Bit $38 Read/Write Initial value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 TOV0 R/W 0 0 R 0 TIFR

Bits 7..2 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.
Bit 1 - TOV0 : Timer/Counter0 Overflow Flag:

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by writing a logic one to the flag. When the SREG Ibit, and TOIE0 (Timer/Counter0 Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is executed.
Bit 0 - Res: Reserved bit:

This bits is a reserved bit in the AT90S1200 and always reads zero. EXTERNAL INTERRUPTS The external interrupt is triggered by the INT0 pin. The interrupt can trigger on rising edge, falling edge or level. This is set up as described in the specification for the MCU control register - MCUCR. When INT0 is level triggered, the interrupt is pending as long as INT0 is held low. The interrupt is triggered even if INT0 is configured as an output. This provides a way to generate a software interrupt. The interrupt flag can not be directly accessed by the user. If an external edge triggered interrupt is suspected to be pending, the flag can be cleared as follows. 1. Disable the external interrupt by clearing the INT0 flag in GIMSK. 2. Select level triggered interrupt. 3. Select desired interrupt edge. 4. Re-enable the external interrupt by setting INT0 in GIMSK. INTERRUPT RESPONSE TIME The interrupt execution response for all the enabled AVR interrupts is 4 clock cycles minimum. After the 4 clock cycles the program vector address for the actual interrupt handling routine is executed. During this 4 clock cycle period, the Program Counter (9 bits) is pushed onto the Stack. The vector is a relative jump to the interrupt routine, and this jump takes 2 clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed before the interrupt is served.

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AT90S1200

AT90S1200
A return from an interrupt handling routine takes 4 clock cycles. During these 4 clock cycles, the Program Counter (9 bits) is popped back from the Stack. When AVR exits from an interrupt, it will always return to the main program and execute one more instruction before any pending interrupt is served. Note that the Status Register - SREG - is not handled by the AVR hardware, neither for interrupts nor for subroutines. For the routines requiring a storage of the SREG, this must be performed by user software. Note that the Subroutine and Interrupt Stack is a 3-level true hardware stack, and if more than 3 nested subroutines and interrupts are executed, only the most recent 3 return addresses are stored. THE MCU CONTROL REGISTER - MCUCR The MCU Control Register contains general microcontroller control bits for general MCU control functions.
Bit $35 Read/Write Initial value 7 R 0 6 R 0 5 SE R/W 0 4 SM R/W 0 3 R 0 2 R 0 1 ISC01 R/W 0 0 ISC00 R/W 0 MCUCR

Bits 7, 6 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.
Bit 5 - SE : Sleep Enable:

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmers purpose, it is recommended to set the Sleep Enable SE bit just before the execution of the SLEEP instruction.
Bit 4 - SM : Sleep Mode:

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle Mode is selected as Sleep Mode. When SM is set (one), Power Down mode is selected as sleep mode. For details, refer to the paragraph "Sleep Modes" below.
Bits 3, 2 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.
Bits 1, 0 - ISC01, ISC00 : Interrupt Sense Control 0 bit 1 and bit 0:

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corresponding interrupt mask in the GIMSK register is set. The level and edges on the external INT0 pin that activate the interrupt are defined as:
Table 4. Interrupt 0 Sense Control
ISC01 0 0 1 1 ISC00 0 1 0 1 Description The low level of INT0 generates an interrupt request. Reserved The falling edge of INT0 generates an interrupt request. The rising edge of INT0 generates an interrupt request.

Note: When changing the ISC10/ISC00 bits, INT0 must be disabled by clearing its Interrupt Enable bit in the GIMSK Register. Otherwise an interrupt can occur when the bits are changed.

Sleep Modes
To enter the sleep modes, the SE bit in MCUCR must be set (one) and a SLEEP instruction must be executed. If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU awakes, executes the interrupt routine, and resumes execution from the instruction following SLEEP. The contents of the register file and the I/O memory are unaltered. If a reset occurs during sleep mode, the MCU wakes up and executes from the Reset vector. Note that if a level triggered interrupt is used for wake-up from power down, the low level must be held for a time longer than the oscillator start-up time of 16 ms. Otherwise, the interrupt flag may return to zero before the MCU starts executing.

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IDLE MODE When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle Mode stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt system to continue operating. This enables the MCU to wake up from external triggered interrupts as well as internal ones like Timer Overflow interrupt and watchdog reset. If wakeup from the Analog Comparator interrupt is not required, the analog comparator can be powered down by setting the ACD-bit in the Analog Comparator Control and Status register - ACSR. This will reduce power consumption during Idle Mode. POWER DOWN MODE When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power Down Mode. In this mode, the external oscillator is stopped. The user can select whether the watchdog shall be enabled during power-down mode. If the watchdog is enabled, it will wake up the MCU when the Watchdog Time-out period expires. If the watchdog is disabled, only an external reset or an external level triggered interrupt can wake up the MCU.

Timer / Counter
The AT90S1200 provides one general purpose 8-bit Timer/Counter. The Timer/Counter gets the prescaled clock from the 10-bit prescaling timer. The Timer/Counter can either be used as a timer with an internal clock timebase or as a counter with an external pin connection which triggers the counting.

The Timer/Counter Prescaler
Figure 19 shows the general Timer/Counter prescaler.

Figure 19. Timer/Counter0 Prescaler The four different prescaled selections are: CK/8, CK/64, CK/256 and CK/1024 where CK is the oscillator clock. For the Timer/Counter, added selections as CK, external source and stop, can be selected as clock sources.

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AT90S1200

AT90S1200
The 8-bit Timer/Counter0
Figure 20 shows the block diagram for Timer/Counter0.

Figure 20. Timer/Counter 0 Block Diagram The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK, or an external pin. In addition it can be stopped as described in the specification for the Timer/Counter0 Control Register - TCCR0. The overflow status flag is found in the Timer/Counter Interrupt Flag Register - TIFR. Control signals are found in the Timer/Counter0 Control Register - TCCR0. The interrupt enable/disable settings for Timer/Counter0 are found in the Timer/Counter Interrupt Mask Register - TIMSK. When Timer/Counter0 is externally clocked, the external signal is synchronized with the oscillator frequency of the CPU. To assure proper sampling of the external clock, the minimum time between two external clock transitions must be at least one internal CPU clock period. The external clock signal is sampled on the rising edge of the internal CPU clock. The 8-bit Timer/Counter0 features both a high resolution and a high accuracy usage with the lower prescaling opportunities. Similarly, the high prescaling opportunities make the Timer/Counter0 useful for lower speed functions or exact timing functions with infrequent actions. THE TIMER/COUNTER0 CONTROL REGISTER - TCCR0
Bit $33 Read/Write Initial value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 CS02 R/W 0 1 CS01 R/W 0 0 CS00 R/W 0 TCCR0

Bits 7..3 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero.
Bits 2,1,0 - CS02, CS01, CS00 : Clock Select0, bit 2,1 and 0:

The Clock Select0 bits 2,1 and 0 define the prescaling source of Timer0.

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Table 5. Clock 0 Prescale Select
CS02 0 0 0 0 1 1 1 1 CS01 0 0 1 1 0 0 1 1 CS00 0 1 0 1 0 1 0 1 Description Stop, the Timer/Counter0 is stopped. CK CK / 8 CK / 64 CK / 256 CK / 1024 External Pin T0, falling edge External Pin T0, rising edge

The Stop condition provides a Timer Enable/Disable function. The CK down divided modes are scaled directly from the CK oscillator clock. If the external pin modes are used, the corresponding setup must be performed in the actual data direction control register (cleared to zero gives an input pin).
Bits 5..3 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and always read zero. THE TIMER COUNTER 0 - TCNT0
Bit $32 Read/Write Initial value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 TCNT0

The Timer/Counter0 is realized as an up-counter with read and write access. If the Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues counting in the timer clock cycle following the write operation.

2-22

AT90S1200

AT90S1200
The Watchdog Timer
The Watchdog Timer is clocked from a separate on-chip oscillator which runs at 1MHz. By controlling the Watchdog Timer prescaler, the Watchdog reset interval can be adjusted from 16 to 2048 cycles. Refer to RC Oscillator Frequency graph on page 2-46. These values apply at VCC = 5V. See characterization data for RC oscillator frequency at other VCC voltages. The WDR - Watchdog Reset - instruction resets the Watchdog Timer. Eight different clock cycle periods can be selected to determine the maximum period between two WDR instructions to avoid that the Watchdog Timer resets the MCU. If the reset period expires without another WDR instruction, the AT90S1200 resets and executes from the reset vector. For timing details on the Watchdog reset, refer to Page 2-17.

Figure 21. Watchdog Timer THE WATCHDOG TIMER CONTROL REGISTER - WDTCR
Bit $21 Read/Write Initial value 7 R 0 6 R 0 5 R 0 4 R 0 3 WDE R/W 0 2 WDP2 R/W 0 1 WDP1 R/W 0 0 WDP0 R/W 0 WDTCR

Bits 7..4 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and will always read as zero.
Bit 3 - WDE : Watchdog Enable:

When the WDE is set (one) the Watchdog Timer is enabled, and if the WDE is cleared (zero) the Watchdog Timer function is disabled.
Bits 2..0 - WDP2..0 : Watchdog Timer Prescaler 2,1 and 0:

The WDP2..0 determine the Watchdog Timer prescaling when the Watchdog Timer is enabled. The different prescaling values and their corresponding Timeout Periods are shown in Table 6.
Table 6. Watchdog Timer Prescale Select (Typical Values at VCC = 5.0V)
WDP2 0 0 0 0 1 1 1 1 WDP1 0 0 1 1 0 0 1 1 WDP0 0 1 0 1 0 1 0 1 Timeout Period 16 cycles 32 cycles 64 cycles 128 cycles 256 cycles 512 cycles 1024 cycles 2048 cycles

2-23

EEPROM Read/Write Access
The EEPROM access registers are accessible in the I/O space. The write access time is in the range of 2.5 - 4ms, depending on the V CC voltages. A self-timing function, however, lets the user software detect when the next byte can be written. An EEPROM brown-out detection prevents writing to the EEPROM if VCC is below a certain level. When the EEPROM is read or written, the CPU is halted for two clock cycles before the next instruction is executed. THE EEPROM ADDRESS REGISTER - EEAR
Bit $1E Read/Write Initial value 7 R 0 6 R 0 5 EEAR5 R/W 0 4 EEAR4 R/W 0 3 EEAR3 R/W 0 2 EEAR2 R/W 0 1 EEAR1 R/W 0 0 EEAR0 R/W 0 EEAR

Bit 7,6 - Res : Reserved bits:

These bits are reserved bit in the AT90S1200 and will always read as zero.
Bits 5..0 - EEAR..0 : EEPROM Address:

The EEPROM Address Register - EEAR5..0 - specifies the EEPROM address in the 64-byte EEPROM space. The EEPROM data bytes are addressed linearly between 0 and 63. THE EEPROM DATA REGISTER - EEDR
Bit $1D Read/Write Initial value 7 MSB R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 6 5 4 3 2 1 0 LSB R/W 0 EEDR

Bits 7..0 - EEDR7..0 : EEPROM Data:

For the EEPROM write operation, the EEDR register contains the data to be written to the EEPROM in the address given by the EEAR register. For the EEPROM read operation, the EEDR contains the data read out from the EEPROM at the address given by EEAR. THE EEPROM CONTROL REGISTER - EECR
Bit $1C Read/Write Initial value 7 R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 1 EEWE R/W 0 0 EERE R/W 0 EECR

Bits 7..2 - Res : Reserved bits:

These bits are reserved bits in the AT90S1200 and will always be read as zero.
Bit 1 - EEWE : EEPROM Write Enable:

The EEPROM Write Enable Signal EEWE is the write strobe to the EEPROM. When address and data are correctly set up, the EEWE bit must be set to write the value into the EEPROM. When the write access time (typically 2.5ms at Vcc=5V and 4ms at VCC = 2.7V) has elapsed, the EEWE bit is cleared (zero) by hardware. The user software can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is halted for two cycles before the next instruction is executed.
Bit 0 - EERE : EEPROM Read Enable:

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct address is set up in the EEAR register, the EERE bit must be set. When the EERE bit is cleared (zero) by hardware, requested data is found in the EEDR register. The EEPROM read access takes one instruction and there is no need to poll the EERE bit. When EERE has been set, the CPU is halted for two cycles before the next instruction is executed.

2-24

AT90S1200

AT90S1200
The Analog Comparator
The analog comparator compares the input values on the positive pin PB0 (AIN0) and the negative pin PB1 (AIN1). When the voltage on the positive pin PB0 (AIN0) is higher than the voltage on the negative pin PB1 (AIN1), the Analog Comparator Output, ACO is set (one). The comparator's output can be set to trigger the Analog Comparator interrupt. The user can select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown in Figure 22.

Figure 22. Analog Comparator Block Diagram

THE ANALOG COMPARATOR CONTROL AND STATUS REGISTER - ACSR
Bit $08 Read/Write Initial value 7 ACD R/W 0 6 R 0 5 ACO R 0 4 ACI R/W 0 3 ACIE R/W 0 2 R 0 1 ACIS1 R/W 0 0 ACIS0 R/W 0 ACSR

Bit 7 - ACD : Analog Comparator Disable

When this bit is set(one), the power to the analog comparator is switched off. This bit can be set at any time to turn off the analog comparator. It is most commonly used if power consumption during Idle Mode is critical, and wake-up from the analog comparator is not required. When changing the ACD bit, the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is changed.
Bit 6 - Res : Reserved bit:

This bit is a reserved bit in the AT90S1200 and will always read as zero.
Bit 5 - ACO : Analog Comparator Output:

ACO is directly connected to the comparator output.
Bit 4 - ACI : Analog Comparator Interrupt Flag:

This bit is set (one) when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator Interrupt routine is executed if the ACIE bit is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when executing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
Bit 3 - ACIE : Analog Comparator Interrupt Enable:

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the analog comparator interrupt is activated. When cleared (zero), the interrupt is disabled.
Bit 2 - Res : Reserved bit:

This bit is a reserved bit in the AT90S1200 and will always read as zero.

2-25

Bits 1,0 - ACIS1, ACIS0 : Analog Comparator Interrupt Mode Select:

These bits determine which comparator events that trigger the Analog Comparator interrupt. The different settings are shown in Table 7.
Table 7. ACIS1/ACIS0 Settings
ACIS1 0 0 1 1 ACIS0 0 1 0 1 Interrupt Mode Comparator Interrupt on Output Toggle Reserved Comparator Interrupt on Falling Output Edge Comparator Interrupt on Rising Output Edge

Note: When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by clearing its Interrupt Enable bit in the ACSR register. Otherwise an interrupt can occur when the bits are changed.

I/O-Ports
Port B
Port B is an 8-bit bi-directional I/O port. Three data memory address locations are allocated for the Port B, one each for the Data Register - PORTB ($18), Data Direction Register - DDRB ($17) and the Port B Input Pins - PINB ($16). The Port B Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. All port pins have individually selectable pullups. The Port B output buffers can sink 20mA and thus drive LED displays directly. When pins PB0 to PB7 are used as inputs and are externally pulled low, they will source current (IIL) if the internal pullups are activated. The Port B pins with alternate functions are shown in the following table:
Table 8. Port B Pins Alternate Functions
Port Pin PB0 PB1 PB5 PB6 PB7 Alternate Functions AIN0 (Analog comparator positive input) AIN1 (Analog comparator negative input) MOSI (Data input line for memory downloading) MISO (Data output line for memory uploading) SCK (Serial clock input)

When the pins are used for the alternate function, the DDRB and PORTB register has to be set according to the alternate function description. THE PORTB DATA REGISTER - PORTB
Bit $18 Read/Write Initial value 7 PORTB7 R/W 0 6 PORTB6 R/W 0 5 PORTB5 R/W 0 4 PORTB4 R/W 0 3 PORTB3 R/W 0 2 PORTB2 R/W 0 1 PORTB1 R/W 0 0 PORTB0 R/W 0 PORTB

2-26

AT90S1200

AT90S1200
THE PORT B DATA DIRECTION REGISTER - DDRB
Bit $17 Read/Write Initial value 7 DDB7 R/W 0 6 DDB6 R/W 0 5 DDB5 R/W 0 4 DDB4 R/W 0 3 DDB3 R/W 0 2 DDB2 R/W 0 1 DDB1 R/W 0 0 DDB0 R/W 0 DDRB

THE PORT B INPUT PIN ADDRESS - PINB
Bit $16 Read/Write Initial value 7 PINB7 R Hi-Z 6 PINB6 R Hi-Z 5 PINB5 R Hi-Z 4 PINB4 R Hi-Z 3 PINB3 R Hi-Z 2 PINB2 R Hi-Z 1 PINB1 R Hi-Z 0 PINB0 R Hi-Z PINB

The Port B Input Pins address - PINB - is not a register, and this address enables access to the physical value on each Port B pin. When reading PORTB, the PORTB Data Latch is read, and when reading PINB, the logical values present on the pins are read. PORTB AS GENERAL DIGITAL I/O All 8 bits in port B are equal when used as digital I/O pins. PBn, General I/O pin: The DDBn bit in the DDRB register selects the direction of this pin, if DDBn is set (one), PBn is configured as an output pin. If DDBn is cleared (zero), PBn is configured as an input pin. If PORTBn is set (one) and the pin is configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, PORTBn has to be cleared (zero) or the pin has to be configured as an output pin.
Table 9. DDBn Effect on PORTB Pins
DDBn 0 0 1 1 PORTBn 0 1 0 1 I/O Input Input Output Output Pull up No Yes No No Comment Tri-state (Hi-Z) PBn will source current (IIL) if ext. pulled low. Push-Pull Zero Output Push-Pull One Output

n: 7,6...0, pin number. ALTERNATE FUNCTIONS OF PORTB The alternate pin functions of Port B are:
SCK - PORTB, Bit 7:

SCK, Clock input pin for Memory up/downloading.
MISO - PORTB, Bit 6:

MISO, Data output pin for Memory uploading.
MOSI - PORTB, Bit 5:

MOSI, Data input pin for Memory downloading.
AIN1 - PORTB, Bit 1:

AIN1, Analog Comparator Negative Input. When configured as an input (DDB1 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB1 is cleared (zero)), this pin also serves as the negative input of the on-chip analog comparator.
AIN0 - PORTB, Bit 0:

AIN0, Analog Comparator Positive Input. When configured as an input (DDB0 is cleared (zero)) and with the internal MOS pull up resistor switched off (PB0 is cleared (zero)), this pin also serves as the positive input of the on-chip analog comparator.

2-27

PORT B SCHEMATICS Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.

Figure 23. PORTB Schematic Diagram (pins PB0 and PB1)

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AT90S1200

AT90S1200

Figure 24. PORTB Schematic Diagram (Pins PB2, PB3 and PB4)

Figure 25. PORTB Schematic Diagram, Pin PB5 2-29

Figure 26. PORTB Schematic Diagram, Pin PB6

Figure 27. PORTB Schematic Diagram, Pin PB7 2-30

AT90S1200

AT90S1200
Port D
Three data memory address locations are allocated for the Port D, one each for the Data Register - PORTD ($12), Data Direction Register - DDRD ($11) and the Port D Input Pins - PIND ($10). The Port D Input Pins address is read only, while the Data Register and the Data Direction Register are read/write. Port D has seven bi-directional I/O pins with internal pullups, PD6..PD0. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current (IIL) if the pullups are activated. Some Port D pins have alternate functions as shown in the following table:
Table 10. Port D Pins Alternate Functions
Port Pin PD2 PD4 Alternate Function INT0 (External interrupt 0 input) T0 (Timer/Counter 0 external input)

THE PORTD DATA REGISTER - PORTD
Bit $12 Read/Write Initial value 7 R 0 6 PORTD6 R/W 0 5 PORTD5 R/W 0 4 PORTD4 R/W 0 3 PORTD3 R/W 0 2 PORTD2 R/W 0 1 PORTD1 R/W 0 0 PORTD0 R/W 0 PORTD

THE PORT D DATA DIRECTION REGISTER - DDRD
Bit $11 Read/Write Initial value 7 R 0 6 DDD6 R/W 0 5 DDD5 R/W 0 4 DDD4 R/W 0 3 DDD3 R/W 0 2 DDD2 R/W 0 1 DDD1 R/W 0 0 DDD0 R/W 0 DDRD

THE PORT D INPUT PINS ADDRESS - PIND
Bit $10 Read/Write Initial value 7 R 0 6 PIND6 R Hi-Z 5 PIND5 R Hi-Z 4 PIND4 R Hi-Z 3 PIND3 R Hi-Z 2 PIND2 R Hi-Z 1 PIND1 R Hi-Z 0 PIND0 R Hi-Z PIND

The Port D Input Pins address - PIND - is not a register, and this address enables access to the physical value on each Port D pin. When reading PORTD, the PORTD Data Latch is read, and when reading PIND, the logical values present on the pins are read. PORTD AS GENERAL DIGITAL I/O PDn, General I/O pin: The DDDn bit in the DDRD register selects the direction of this pin. If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn is configured as an input pin. If PORTDn is set (one) when DDDn is configured as an input pin, the MOS pull up resistor is activated. To switch the pull up resistor off, the PORTDn bit has to be cleared (zero) or the pin has to be configured as an output pin.
Table 11. DDDn Bits Effect on Port D Pins
DDDn 0 0 1 1 PORTDn 0 1 0 1 I/O Input Input Output Output Pull up No Yes No No Comment Tri-state (Hi-Z) PDn will source current (IIL) if ext. pulled low. Push-Pull Zero Output Push-Pull One Output

n: 6...0, pin number.

2-31

ALTERNATE FUNCTIONS FOR PORTD The alternate functions of Port D are:
T0 - PORTD, Bit 4:

T0, Timer/Counter0 clock source. See the Timer description for further details.
INT0 - PORTD, Bit 2:

INT0, External Interrupt source 0. See the interrupt description for further details. PORTD SCHEMATICS Note that all port pins are synchronized. The synchronization latches are however, not shown in the figures.

Figure 28. PORTD Schematic Diagram (Pins PD0, PD1, PD3, PD5 and PD6)

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AT90S1200

AT90S1200

Figure 29. PORTD Schematic Diagram (Pin PD2)

Figure 30. PORTD Schematic Diagram (Pin PD4) 2-33

Memory Programming
Program Memory Lock Bits
The AT90S1200 MCU provides two lock bits which can be left unprogrammed (`1') or can be programmed (`0') to obtain the additional features listed in Table 12.
Table 12. Lock Bit Protection Modes
Program Lock Bits Mode 1 LB1 1 LB2 1 No program lock features Further programming of the Flash is disabled Protection Type

2

0

1

3

0

0

Same as mode 2, but verify is also disabled.

Note: The Lock Bits can only be erased with the Chip Erase operation.

Fuse Bits
The Fuse bits in the AT90S1200 are RCEN and SPIEN. When RCEN is programmed (`0'), MCU clocking from the internal RC oscillator is selected. Default value is erased (`1'). Order AT90S1200A to get parts with this bit programmed. When SPIEN is programmed (`0'), Serial Programming Mode is enabled. Default value is programmed (`0'). These bits are not accessible in Serial Programming Mode and are not changed by a chip erase.

Device Code
All Atmel microcontrollers have a three-byte signature code which identifies the device. This code can be read in both serial and parallel mode. The three bytes reside in a separate address space, and for the AT90S1200 they are: 1. $000: $1E (indicates manufactured by Atmel) 2. $001: $90 (indicates 1 kB Flash memory) 3. $002: $01 (indicates 90S1200 device when $001 is $90)

Programming the Flash and EEPROM
Atmel's AT90S1200 offers 1K bytes of in-system reprogrammable Flash Program memory and 64 bytes of EEPROM Data memory. The AT90S1200 is normally shipped with the on-chip Flash Program memory and EEPROM Data memory arrays in the erased state (i.e. contents = $FF) and ready to be programmed. This device supports a High-Voltage (12V) Parallel programming mode and a Low-Voltage Serial programming mode. The +12V is used for programming enable only, and no current of significance is drawn by this pin. The serial programming mode provides a convenient way to download the Program and Data into the AT90S1200 inside the user's system. The Program and Data memory arrays on the AT90S1200 are programmed byte-by-byte in either programming modes. For the EEPROM, an auto-erase cycle is provided in the serial programming mode.

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AT90S1200

AT90S1200
Parallel Programming
This section describes how to parallel program and verify Flash Program memory, EEPROM Data memory + Program Memory Lock bits and Fuse bits in the AT90S1200.

Figure 31. Parallel Programming SIGNAL NAMES In this section, some pins of the AT90S1200 are referenced by signal names describing their functionality during parallel programming rather than their pin names. Pins not described in the following table are referenced by pin names.
Table 13. Pin Name Mapping
Signal Name in Programming Mode RDY/BSY OE WR BS XA0 XA1

Pin Name PD1 PD2 PD3 PD4 PD5 PD6

I/O O I I I I I

Function 0: Device is busy programming, 1: Device is ready for new command Output Enable (Active Low) Write Pulse (Active Low) Byte Select XTAL Action Bit 0 XTAL Action Bit 1

The XA1/XA0 bits determine the action taken when the XTAL1 pin is given a positive pulse. The bit settings are shown in the following table:
Table 14. XA1 and XA0 Coding
XA1 0 0 1 1 XA0 0 1 0 1 Action when XTAL1 is Pulsed Load Flash or EEPROM Address (High or Low address byte for Flash determined by BS) Load Data (High or Low data byte for Flash determined by BS) Load Command No Action, Idle

2-35

When pulsing WR or OE, the command loaded determines the action on input or output. The command is a byte where the different bits are assigned functions as shown in the following table:
Table 15. Command Byte Bit Coding
Bit# 7 6 5 4 3 2 1 0 Meaning when Set Chip Erase Write Fuse Bits. Located in the data byte at the following bit positions: D5: SPI Fuse, D0: RCEN Fuse (Note: write `0' to program, `1' to erase) Write Lock Bits. Located in the data byte at the following bit positions: D2: LB2, D1: LB1 (Note: write `0' to program) Write Flash or EEPROM (determined by bit 0) Read signature row Read Lock and Fuse Bits. Located in the data byte at the following bits positions: D7: LB1, D6: LB2, D5: SPI Fuse, D0: RCEN Fuse Read from Flash or EEPROM (determined by bit 0) 0: Flash Access, 1: EEPROM Access

ENTER PROGRAMMING MODE The following algorithm puts the device in parallel programming mode: 1. Apply 4.5 - 5.5V between VCC and GND. 2. Set the RESET and BS pin to `0' and wait at least 100 ns. 3. Apply 12V to RESET and wait at least 100ns before changing BS. CHIP ERASE The chip erase will erase the Flash and EEPROM memories plus Lock bits. The lock bits are not reset until the program memory has been completely erased. The Fuse bits are not changed. |A chip erase must be performed before the chip is programmed. Load Command "Chip Erase" 1. Set XA1, XA0 to `10'. This enables command loading. 2. Set BS to `0'. 3. Set PB(7:0) to `1000 0000'. This is the command for Chip erase. 4. Give XTAL1 a positive pulse. This loads the command, and starts the erase of the Flash and EEPROM arrays. After pulsing XTAL1, give WR a negative pulse to enable lock bit erase at the end of the erase cycle. Then wait at least 10 ms for the chip erase cycle to finish. Chip erase does not generate any activity on the RDY/BSY signal. PROGRAMMING THE FLASH Load Command "Program Flash" 1. Set XA1, XA0 to `10'. This enables command loading. 2. Set BS to `0' 3. Set PB(7:0) to `0001 0000'. This is the command for Flash programming. 4. Give XTAL1 a positive pulse. This loads the command. Load Address Low byte 1. Set XA1, XA0 to `00'. This enables address loading. 2. Set BS to `0'. This selects Low address. 3. Set PB(7:0) = Address Low byte ($00 - $FF) 4. Give XTAL1 a positive pulse. This loads the Address Low byte.

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AT90S1200

AT90S1200
Load Address High byte 1. Set XA1, XA0 to `00'. This enables address loading. 2. Set BS to `1'. This selects High address. 3. Set PB(7:0) = Address High byte ($00 - $01) 4. Give XTAL1 a positive pulse. This loads the Address High byte. Load Data byte 1. Set XA1, XA0 to `01'. This enables data loading. 2. Set PB(7:0) = Data Low byte ($00 - $FF) 3. Give XTAL1 a positive pulse. This loads the Data Low byte. Write Data Low byte 1. Set BS to `0'. This selects Low data. 2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. Load Data byte 1. Set XA1, XA0 to `01'. This enables data loading. 2. Set PB(7:0) = Data High byte ($00 - $FF) 3. Give XTAL1 a positive pulse. This loads the Data High byte. Write Data High byte 1. Set BS to `1'. This selects high data. 2. Give WR a positive pulse. This starts programming of the data byte. RDY/BSY goes low. 3. Wait until RDY/BSY goes high to program the next byte. The loaded command and address are retained in the device during programming. To simplify programming, the following should be considered. ˇ The command for Flash programming needs only be loaded before programming of the first byte. ˇ Address High byte needs only be loaded before programming a new 256 word page in the Flash.

2-37

Figure 32. Programming Flash Low Byte

Figure 33. Programming Flash High Byte PROGRAMMING THE EEPROM The programming algorithm for the EEPROM data memory is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0001 0001'. 2. Load Low EEPROM Address ($00 - $3F) 3. Load Low EEPROM Data ($00 - $FF) 4. Give WR a negative pulse and wait for RDY/BSY to go high. The Command needs only be loaded before programming the first byte.

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AT90S1200

AT90S1200
READING THE FLASH The algorithm for reading the Flash memory is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0000 0010'. 2. Load Low Address ($00 - $FF) 3. Load High Address ($00 - $01) 4. Set OE to `0', and BS to `0'. The Low Data byte can now be read at PB(7:0) 5. Set BS to `1'. The High Data byte can now be read from PB(7:0) 6. Set OE to `1'. The Command needs only be loaded before reading the first byte. READING THE EEPROM The algorithm for reading the EEPROM memory is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0000 0011'. 2. Load Low Address ($00 - $3F) 3. Set OE to `0', and BS to `0'. The EEPROM Data byte can now be read at PB(7:0) 4. Set OE to `1'. The Command needs only be loaded before reading the first byte. PROGRAMMING THE FUSE BITS The algorithm for programming the Fuse bits is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0100 0000'. 2. Load Data. Bit 5 = `0' programs the SPI Fuse bit. Bit 5 = `1' erases the SPI Fuse bit. Bit 0 = `0' programs the RCEN Fuse bit. Bit 0 = `1' erases the RCEN Fuse bit. 3. Give WR a negative pulse and wait for RDY/BSY to go high. IMPORTANT! WR must be held low for at least 1 ms. PROGRAMMING THE LOCK BITS The algorithm for programming the Lock bits is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0010 0000'. 2. Load Data. Bit 2 = '0' programs Lock Bit2 Bit 1 = '0' programs Lock Bit1 3. Give WR a negative pulse and wait for RDY/BSY to go high. The lock bits can only be cleared by executing a chip erase.

2-39

READING THE FUSE AND LOCK BITS The algorithm for reading the Fuse and Lock bits is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0000 0100'. 2. Set OE to `0', and BS to `1'. The Status of Fuses an Lock bits can now be read at PB(7:0) Bit 7: Lock Bit1 (`0' means programmed) Bit 6: Lock Bit2 (`0' means programmed) Bit 5: SPI Fuse (`0' means programmed) Bit 0: RCEN Fuse (`0' means programmed) 3. Set OE to `1'. Observe especially that BS needs to be set to `1'. READING THE SIGNATURE BYTES The algorithm for reading the Signature bytes is as follows (refer to Flash Programming for details on Command, Address and Data loading): 1. Load Command `0000 1000'. 2. Load Low address ($00 - $02) Set OE to `0', and BS to `0'. The Selected Signature byte can now be read at PB(7:0) 3. Set OE to `1'. The command needs only be programmed before reading the first byte.

Serial Downloading
Both the Program and Data memory arrays can be programmed using the serial SPI bus while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (output). After RESET is set low, the Programming Enable instruction needs to be executed first before program/erase operations can be executed. When programming the EEPROM, an auto-erase cycle is built into the self-timed programming operation (in the serial mode ONLY) and there is no need to first execute the Chip Erase instruction. The Chip Erase operation turns the content of every memory location in both the Program and EEPROM arrays into $FF. The Program and EEPROM memory arrays have separate address spaces: $000 to $3FF for Program Flash memory and $000 to $03F for EEPROM Data memory. Either an external system clock is supplied at pin XTAL1 or a crystal needs to be connected across pins XTAL1 and XTAL2. The minimum low and high periods for the serial clock (SCK) input are defined as follows:

Low: High:

> 1 XTAL1 clock cycle > 4 XTAL1 clock cycles

SERIAL PROGRAMMING ALGORITHM To program and verify the AT90S1200 in the serial programming mode, the following sequence is recommended (See four byte instruction formats in Table 16): 1. Power-up sequence: Apply power between VCC and GND while RESET and SCK are set to `0'. (If the programmer can not guarantee that SCK is held low during power-up, RESET must be given a positive pulse after SCK has been set to `0'.) If a crystal is not connected across pins XTAL1 and XTAL2, apply a 0 to 16 MHz clock to the XTAL1 pin. 2. Wait for at least 20 ms and enable serial programming by sending the Programming Enable serial instruction to pin MOSI/PB5. Refer to the above section for minimum low and high periods for the serial clock input, SCK. 3. If a chip erase is performed (must be done to erase the Flash), wait 10ms, give RESET a positive pulse and start over again from Step 2. 4. The Flash or EEPROM array is programmed one byte at a time by supplying the address and data together with the appropriate Write instruction. An EEPROM memory location is first automatically erased before new data is written. The next byte can be written after 4 ms.

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AT90S1200

AT90S1200
5. Any memory location can be verified by using the Read instruction which returns the content at the selected address at serial output MISO/PB6. At the end of the programming session, RESET can be set high to commence normal operation. 6. Power-off sequence (if needed): Set XTAL1 to `0' (if a crystal is not used). Set RESET to `1'. Turn VCC power off.
Table 16. Serial Programming Instruction Set AT90S1200
Instruction Format Instruction Byte 1 Programming Enable Chip Erase Read Program Memory Write Program Memory Read EEPROM Memory Write EEPROM Memory Write Lock Bits Read Device Code 1010 1100 1010 1100 0010 H000 0100 H000 1010 0000 1100 0000 1010 1100 0011 0000 Byte 2 0101 0011 100x xxxx 0000 000a 0000 000a 0000 0000 0000 0000 111x x21x xxxx xxxx Byte 3 xxxx xxxx xxxx xxxx bbbb bbbb bbbb bbbb xxbb bbbb xxbb bbbb xxxx xxxx xxxx xxbb Byte4 xxxx xxxx xxxx xxxx oooo oooo iiii iiii oooo oooo iiii iiii xxxx xxxx oooo oooo Enable Serial Programming after RESET goes low. Chip erase both 1K & 64 byte memory arrays Read H(high or low) data o from Program memory at word address a:b Write H(high or low) data i to Program memory at word address a:b Read data o from EEPROM memory at address b Write data i to EEPROM memory at address b Write lock bits. Set bits 1,2='0' to program lock bits. Read Device Code o from address b. Operation

Notes: a = address high bits b = address low bits H = 0 - Low byte, 1- High byte o = data out i = data in x = don't care 1 = lock bit 1 2 = lock bit 2

Figure 34. Programming and Verify When writing serial data to the AT90S1200, data is clocked on the rising edge of CLK. When reading data from the AT90S1200, data is clocked on the falling edge of CLK. See Figure 35 for an explanation.

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Programming Characteristics

Figure 35. Serial Downloading Waveforms

Absolute Maximum Ratings
Operating Temperature ........................-55°C to +125°C Storage Temperature............................-65°C to +150°C Voltage on any Pin except RESET with respect to Ground ............................ -1.0V to +7.0V Maximum Operating Voltage ...................................6.6V DC Current per I/O Pin ......................................40.0 mA DC Current VCC and GND Pins......................140.0 mA
*NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

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AT90S1200

AT90S1200
DC Characteristics
TA = -40°C to 85°C, VCC = 2.7V to 6.0V (unless otherwise noted)
Symbol VIL VIH VIH1 VOL VOH IOH IIL RRST RI/O Parameter Input Low Voltage Input High Voltage Input High Voltage Output Low Voltage (Ports B, D) Output High Voltage (Ports B,D) Output Source Current (Ports B,D) Output Sink Current (Port B,D) Reset Pull-Up Resistor I/O Pin Pull-Up Resistor Active Mode, 3V, 4MHz Idle Mode 3V, 4MHz ICC Power Supply Current Power Down WDT enabled, 3V Power Down (2) WDT disabled, 3V VACIO IACLK tACPD Analog Comparator Input Offset Voltage Analog Comparator Input Leakage Current Analog Comparator Propagation Delay VCC = 5V VIN = 1V VCC = 2.7V VCC = 4.0V 10 750 500
(2) (1)

Condition

Min -0.5

Typ

Max 0.2 Vcc - 0.1 VCC + 0.5 VCC + 0.5 0.5

Units V V V V V

(Except XTAL1, RESET) (XTAL1, RESET) IIL = 25 mA, VCC = 5V IIL = 15 mA, VCC = 3V IOH = 3 mA, VCC = 5V IOH = 3 mA, VCC = 3V VCC = 5V, VOH = 4.5V VCC = 3V, VOH = 2.7V VCC = 5V, VOL = 0.5V VCC = 3V, VOL = 0.3V

0.2 VCC + 0.9 0.7 VCC

VCC - 0.5 4 2 28 11 100 35 2 500 10 0.15 15 (3) 1(3) 20 500 120

mA

mA k k mA ľA ľA ľA mV nA ns

Notes:

1. Under steady state (non-transient) conditions, IOL must be externally limited as follows: Maximum IOL per port pin: 20mA Maximum total IOL for all output pins: 80mA If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions. 2. Minimum VCC for Power Down is 2V. 3. Value tested to 45°C

2-43

External Clock Drive Waveforms

External Clock Drive
Symbol
1/tCLCL tCLCL tCHCX tCLCX tCLCH tCHCL

Parameter Oscillator Frequency Clock Period High Time Low Time Rise Time Fall Time

VCC = 2.7V to 6.0V
Min 0 250 40 40 10 10 Max 4

VCC = 4.0V to 6.0V
Min 0 62.5 16.7 16.7 4.15 4.15 Max 16

Units
MHz ns ns ns ns ns

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AT90S1200

AT90S1200

2-45

Note:

Charts show typical values.

Ordering Information
Speed (MHz) Power Supply Ordering Code* AT90S1200-4PC AT90S1200-4SC AT90S1200-4YC 4 2.7 - 6.0V AT90S1200-4PI AT90S1200-4SI AT90S1200-4YI AT90S1200-16PC AT90S1200-16SC AT90S1200-16YC 16 4.0 - 6.0V AT90S1200-16PI AT90S1200-16SI AT90S1200-16YI 20P3 20S 20Y Industrial (-40°C to 85°C) 20P3 20S 20Y 20P3 20S 20Y Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Package 20P3 20S 20Y Operation Range Commercial (0°C to 70°C)

* Order AT90S1200A-XXX for devices with the RCEN fuse programmed.

Package Type 20P3 20S 20Y 20 Lead, 0.300" Wide Pl