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Microcontroller
with 4K/8K
Bytes In-System
Programmable Flash
AT90S4434
AT90LS4434
AT90S8535
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Features
· · · ·
Utilizes the AVR ® Enhanced RISC Architecture AVR - High Performance and Low Power RISC Architecture 118 Powerful Instructions - Most Single Clock Cycle Execution 8K bytes of In-System Programmable Flash AT90S/LS8535 4K bytes of In-System Programmable Flash AT90S/LS4434 SPI Serial Interface for In-System Programming Endurance: 1,000 Write/Erase Cycles 512 bytes EEPROM AT90S/LS8535 256 bytes EEPROM AT90S/LS4434 Endurance: 100,000 Write/Erase Cycles 512 bytes Internal SRAM AT90S/LS8535 256 bytes Internal SRAM AT90S/LS4434 8-Channel, 10-Bit ADC 32 x 8 General Purpose Working Registers 32 Programmable I/O Lines Programmable Serial UART VCC: 4.0 - 6.0V AT90S4434/AT90S8535 VCC: 2.7 - 6.0V AT90LS4434/AT90LS8535 Speed Grades: 0 - 8 MHz AT90S4434/AT90S8535, 0 - 4 MHz (AT90LS4434/AT90LS8535 Power-On Reset Circuit Up to 8 MIPS Throughput at 8 MHz RTC with Separate Oscillator and Counter Mode Two 8-Bit Timer/Counters with Separate Prescaler and Compare Mode One 16-Bit Timer/Counter with Separate Prescaler and Compare and Capture Modes 3 PWM channels External and Internal Interrupt Sources Programmable Watchdog Timer with On-Chip Oscillator On-Chip Analog Comparator Three Sleep Modes: Idle, Power Save, and Power Down Programming Lock for Software Security
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8-Bit Microcontroller with 4K/8K Bytes In-System Programmable Flash AT90S4434 AT90LS4434 AT90S8535 AT90LS8535 Advance Information
Description
The AT90S4434/8535 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S4434/8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. (continued)
Pin Configurations
Rev. 1041AS05/98
Note: This is a summary document. For the complete 80 page document, please visit our website at www.atmel.com or e-mail at 1 [email protected] and request literature #1041A.
Block Diagram
PA0 - PA7 PC0 - PC7 VCC
PORTA DRIVERS
PORTC DRIVERS
GND DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC
8-BIT DATA BUS AVCC
ANALOG MUX AGND AREF
ADC OSCILLATOR XTAL1
INTERNAL OSCILLATOR
OSCILLATOR
PROGRAM COUNTER
STACK POINTER
WATCHDOG TIMER
TIMING AND CONTROL
XTAL2 RESET
PROGRAM FLASH
SRAM
MCU CONTROL REGISTER
INSTRUCTION REGISTER
GENERAL PURPOSE REGISTERS
X Y Z
TIMER/ COUNTERS
INSTRUCTION DECODER
INTERRUPT UNIT
CONTROL LINES
ALU
EEPROM
STATUS REGISTER
PROGRAMMING LOGIC
SPI
UART
ANALOG COMPARATOR
DATA REGISTER PORTB
DATA DIR. REG. PORTB
DATA REGISTER PORTD
DATA DIR. REG. PORTD
+ -
PORTB DRIVERS
PORTD DRIVERS
PB0 - PB7
PD0 - PD7
The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs up to ten times faster than conventional CISC microcontrollers. The AT90S4434/8535 provides the following features: 4K/8K bytes of In-System Programmable Flash, 256/512 bytes EEPROM, 256/512 bytes SRAM, 32 general purpose I/O lines, 32 general purpose working registers, RTC, three flexible timer/counters with compare modes, internal and
external interrupts, a programmable serial UART, 8-channel, 10-bit ADC, programmable Watchdog Timer with internal oscillator, an SPI serial port and three software selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM, timer/counters, SPI port and interrupt system to continue functioning. The Power Down mode saves the register contents but freezes the oscillator, disabling all other chip functions until the next interrupt or hardware reset. In Power Save mode, the timer oscillator continues to run, allowing the user to maintain a timer base while the rest of the device is sleeping. The device is manufactured using Atmel's high density non-volatile memory technology. The on-chip ISP Flash
2
AT90S/LS4434 and AT90S/LS8535
AT90S/LS4434 and AT90S/LS8535
allows the program memory to be reprogrammed in-system through an SPI serial interface or by a conventional nonvolatile memory programmer. By combining an 8-bit RISC CPU with In-System Programmable Flash on a monolithic chip, the Atmel AT90S4434/8535 is a powerful microcontroller that provides a highly flexible and cost effective solution to many embedded control applications. The AT90S4434/8535 AVR is supported with a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators, in-circuit emulators, and evaluation kits. Comparison between AT90S4434 and AT90S8535 The AT90S4434 has 4K bytes of In-System Programmable Flash, 256 bytes of EEPROM, and 256 bytes of internal SRAM. The AT90S8535 has 8K bytes of In-System Programmable Flash, 512 bytes of EEPROM, and 512 bytes of internal SRAM. Table 1 summarizes the different memory sizes for the two devices. Table 1. Memory Size Summary
Part AT90S4434 AT90S8535 Flash 4K bytes 8K bytes EEPROM 256 bytes 512 bytes SRAM 256 bytes 512 bytes
Pin Descriptions
VCC Digital supply voltage GND Digital ground Port A (PA7..PA0) Port A is an 8-bit bi-directional I/O port. Port pins can provide internal pull-up resistors (selected for each bit). The Port A output buffers can sink 20mA and can drive LED displays directly. When pins PA0 to PA7 are used as inputs and are externally pulled low, they will source current if the internal pull-up resistors are activated. Port A also serves as the analog inputs to the A/D Converter. Port B (PB7..PB0) Port B is an 8-bit bi-directional I/O pins with internal pull-up resistors. The Port B output buffers can sink 20 mA. As inputs, Port B pins that are externally pulled low will source current if the pull-up resistors are activated. Port B also serves the functions of various special features of the AT90S4434/8535 as listed on page 52. Port C (PC7..PC0)
Port C is an 8-bit bi-directional I/O port with internal pullup resistors. The Port C output buffers can sink 20 mA. As inputs, Port C pins that are externally pulled low will source current if the pull-up resistors are activated. Two Port C pins can alternatively be used as oscillator for Timer/Counter2. Port D (PD7..PD0) Port D is an 8-bit bidirectional I/O port with internal pull-up resistors. The Port D output buffers can sink 20 mA. As inputs, Port D pins that are externally pulled low will source current if the pull-up resistors are activated. Port D also serves the functions of various special features of the AT90S4434/8535 as listed on page 59. RESET Reset input. A low on this pin for two machine cycles while the oscillator is running resets the device. XTAL1 Input to the inverting oscillator amplifier and input to the internal clock operating circuit. XTAL2 Output from the inverting oscillator amplifier AVCC This is the supply voltage pin for the A/D Converter. It should be externally connected to VCC via a low-pass filter. See page 47 for details on operation of the ADC. AREF This is the analog reference input for the A/D Converter. For ADC operations, a voltage in the range AGND to AVCC must be applied to this pin. AGND Analog ground. If the board has a separate analog ground plane, this pin should be connected to this ground plane. Otherwise, connect to GND.
Crystal Oscillators
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be configured for use as an on-chip oscillator, as shown in Figure 1. Either a quartz crystal or a ceramic resonator may be used. To drive the device from an external clock source, XTAL2 should be left unconnected while XTAL1 is driven as shown in Figure 2. For the Timer Oscillator pins, PC6(OSC1) and PC7(OSC2), the crystal is connected directly between the pins. No external capacitors are needed. The oscillator is optimized for use with a 32,768 Hz watch crystal. An external clock signal applied to this pin goes through the same amplifier having a bandwidth of 256 kHz. The external clock signal should therefore be in the interval 0 Hz - 256 kHz.
3
Figure 1. Oscillator Connections
Figure 2. External Clock Drive Configuration
Architectural Overview
The fast-access register file concept contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This means that during one single clock cycle, one Arithmetic Logic Unit (ALU) operation is executed. Two operands are output from the register file, the operation is executed, and the result is stored back in the register file in one clock cycle. Six of the 32 registers can be used as three 16-bits indirect address register pointers for Data Space addressing enabling efficient address calculations. One of the three address pointers is also used as the address pointer for the constant table look up function. These added function registers are the 16-bits X-register, Y-register and Z-register.
Figure 3. The AT90S4434/8535 AVR Enhanced RISC Architecture
AVR AT90S4434/8535 Architecture
Data Bus 8-bit
2K/4K X 16 Program Memory
Program Counter
Status and Control
Interrupt Unit SPI Unit Serial UART 8-bit Timer/Counter
Instruction Register
32 x 8 General Purpose Registrers
Indirect Addressing
Instruction Decoder
Direct Addressing
ALU 16-bit Timer/Counter with PWM 8-bit Timer/Counter with PWM Watchdog Timer Analog to Digital Converter
Control Lines
256/512 x 8 Data SRAM
256/512 x 8 EEPROM 32 I/O Lines
Analog Comparator
4
AT90S/LS4434 and AT90S/LS8535
AT90S/LS4434 and AT90S/LS8535
The ALU supports arithmetic and logic functions between registers or between a constant and a register. Single register operations are also executed in the ALU. Figure 3 shows the AT90S4434/8535 AVR Enhanced RISC microcontroller architecture. In addition to the register operation, the conventional memory addressing modes can be used on the register file as well. This is enabled by the fact that the register file is assigned the 32 lowermost Data Space addresses ($00 $1F), allowing them to be accessed as though they were ordinary memory locations. The I/O memory space contains 64 addresses for CPU peripheral functions as Control Registers, Timer/Counters, A/D-converters, and other I/O functions. The I/O Memory can be accessed directly, or as the Data Space locations following those of the register file, $20 - $5F. The AVR uses a Harvard architecture concept - with separate memories and buses for program and data. The program memory is executed with a single level pipelining. While one instruction is being executed, the next instruction is pre-fetched from the program memory. This concept Figure 4. Memory Maps
Program Memory $000 Data Memory 32 Gen. Purpose $0000 Working Registers $001F $0020 64 I/O Registers Program Flash (2K/4K x 16) $005F $0060
EEPROM (256/512 x 8)
enables instructions to be executed in every clock cycle. The program memory is in-system downloadable Flash memory. With the relative jump and call instructions, the whole 2K/4K address space is directly accessed. Most AVR instructions have a single 16-bit word format. Every program memory address contains a 16- or 32-bit instruction. During interrupts and subroutine calls, the return address program counter (PC) is stored on the stack. The stack is effectively allocated in the general data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. All user programs must initialize the SP in the reset routine (before subroutines or interrupts are executed). The 9-bit stack pointer SP is read/write accessible in the I/O space. The 256/512 bytes data SRAM can be easily accessed through the five different addressing modes supported in the AVR architecture. The memory spaces in the AVR architecture are all linear and regular memory maps.
Data Memory
$0000
Internal SRAM (256/512 x 8)
$1F/$FF
$015F/$025F
$7FF/$FFF
5
AT90S4434/8535 Register Summary
Address
$3F ($5F) $3E ($5E) $3D ($5D) $3C ($5C) $3B ($5B) $3A ($5A) $39 ($59) $38 ($58) $37 ($57) $36 ($56) $35 ($55) $34 ($54) $33 ($53) $32 ($52) $31 ($51) $30 ($50) $2F ($4F) $2E ($4E) $2D ($4D) $2C ($4C) $2B ($4B) $2A ($4A) $29 ($49) $28 ($48) $27 ($47) $26 ($46) $25 ($45) $24 ($44) $23 ($43) $22 ($42) $21 ($41) $20 ($40) $1F ($3F) $1E ($3E) $1D ($3D) $1C ($3C) $1B ($3B) $1A ($3A) $19 ($39) $18 ($38) $17 ($37) $16 ($36) $15 ($35) $14 ($34) $13 ($33) $12 ($32) $11 ($31) $10 ($30) $0F ($2F) $0E ($2E) $0D ($2D) $0C ($2C) $0B ($2B) $0A ($2A) $09 ($29) $08 ($28) $07 ($27) $06 ($26) $05 ($25) $04 ($24) $03 ($20) $02 ($22) $01 ($21) $00 ($20)
Name
SREG SPH SPL Reserved GIMSK GIFR TIMSK TIFR Reserved Reserved MCUCR MCUSR TCCR0 TCNT0 Reserved Reserved TCCR1A TCCR1B TCNT1H TCNT1L OCR1AH OCR1AL OCR1BH OCR1BL ICR1H ICR1L TCCR2 TCNT2 OCR2 ASSR WDTCR Reserved EEARH EEARL EEDR EECR PORTA DDRA PINA PORTB DDRB PINB PORTC DDRC PINC PORTD DDRD PIND SPDR SPSR SPCR UDR USR UCR UBRR ACSR ADMUX ADCSR ADCH ADCL Reserved Reserved Reserved Reserved
Bit 7
I SP7 INT1 INTF1 OCIE2 OCF2
Bit 6
T SP6 INT0 INTF0 TOIE2 TOV2
Bit 5
H SP5 TICIE1 ICF1
Bit 4
S SP4 OCIE1A OCF1A
Bit 3
V SP3 OCIE1B OCF1B
Bit 2
N SP2 TOIE1 TOV1
Bit 1
Z SP9 SP1 -
Bit 0
C SP8 SP0 TOIE0 TOV0
Page
21 22 22 28 28 29 30
SE Timer/Counter0 (8 Bits)
SM1 -
SM0 -
ISC11 -
ISC10 CS02
ISC01 EXTRF CS01
ISC00 PORF CS00
31 27 35 36
COM1A1 COM1A0 COM1B1 COM1B0 ICNC1 ICES1 Timer/Counter1 - Counter Register High Byte Timer/Counter1 - Counter Register Low Byte Timer/Counter1 - Output Compare Register A High Byte Timer/Counter1 - Output Compare Register A Low Byte Timer/Counter1 - Output Compare Register B High Byte Timer/Counter1 - Output Compare Register B Low Byte Timer/Counter1 - Input Capture Register High Byte Timer/Counter1 - Input Capture Register Low Byte PWM2 COM21 COM20 Timer/Counter2 (8 Bits) Timer/Counter2 Output Compare Register WDTOE
CTC1
CS12
PWM11 CS11
PWM10 CS10
CTC2
CS22
CS21
CS20
AS2 WDE
TCN2UB WDP2
OCR2UB WDP1
TCR2UB WDP0 EEAR9 EEAR0 EERE PORTA0 DDA0 PINA0 PORTB0 DDB0 PINB0 PORTC0 DDC0 PINC0 PORTD0 DDD0 PIND0 SPR0 TXB8 ACIS0 MUX0 ADPS0 ADC8 ADC0
38 39 40 40 41 41 41 41 41 41 45 46 46 48 50
EEAR7 EEAR6 EEPROM Data Register PORTA7 PORTA6 DDA7 DDA6 PINA7 PINA6 PORTB7 PORTB6 DDB7 DDB6 PINB7 PINB6 PORTC7 PORTC6 DDC7 DDC6 PINC7 PINC6 PORTD7 PORTD6 DDD7 DDD6 PIND7 PIND6 SPI Data Register SPIF WCOL SPIE SPE UART I/O Data Register RXC TXC RXCIE TXCIE UART Baud Rate Register ACD ADEN ADSC ADC7 ADC6
EEAR5 PORTA5 DDA5 PINA5 PORTB5 DDB5 PINB5 PORTC5 DDC5 PINC5 PORTD5 DDD5 PIND5 DORD UDRE UDRIE ACO ADFR ADC5
EEAR4 PORTA4 DDA4 PINA4 PORTB4 DDB4 PINB4 PORTC4 DDC4 PINC4 PORTD4 DDD4 PIND4 MSTR FE RXEN ACI ADIF ADC4
EEAR3 EERIE PORTA3 DDA3 PINA3 PORTB3 DDB3 PINB3 PORTC3 DDC3 PINC3 PORTD3 DDD3 PIND3 CPOL OR TXEN ACIE ADIE ADC3
EEAR2 EEMWE PORTA2 DDA2 PINA2 PORTB2 DDB2 PINB2 PORTC2 DDC2 PINC2 PORTD2 DDD2 PIND2 CPHA CHR9 ACIC MUX2 ADPS2 ADC2
EEAR1 EEWE PORTA1 DDA1 PINA1 PORTB1 DDB1 PINB1 PORTC1 DDC1 PINC1 PORTD1 DDD1 PIND1 SPR1 RXB8 ACIS1 MUX1 ADPS1 ADC9 ADC1
51 51 52 70 70 70 72 72 72 78 78 78 81 81 81 57 56 56 60 60 61 67 67 67 68 68
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AT90S/LS4434
AT90S/LS4434 and AT90S/LS8535
AT90S4434/8535 Instruction Set Summary
Mnemonics Operands Description Operation
Rd Rd + Rr Rd Rd + Rr + C Rdh:Rdl Rdh:Rdl + K Rd Rd - Rr Rd Rd - K Rd Rd - Rr - C Rd Rd - K - C Rdh:Rdl Rdh:Rdl - K Rd Rd · Rr Rd Rd · K Rd Rd v Rr Rd Rd v K Rd Rd Rr Rd $FF - Rd Rd $00 - Rd Rd Rd v K Rd Rd · ($FF - K) Rd Rd + 1 Rd Rd - 1 Rd Rd · Rd Rd Rd Rd Rd $FF PC PC + k + 1 PC Z PC PC + k + 1 PC Z PC STACK PC STACK if (Rd = Rr) PC PC + 2 or 3 Rd - Rr Rd - Rr - C Rd - K if (Rr(b)=0) PC PC + 2 or 3 if (Rr(b)=1) PC PC + 2 or 3 if (P(b)=0) PC PC + 2 or 3 if (P(b)=1) PC PC + 2 or 3 if (SREG(s) = 1) then PCPC+k + 1 if (SREG(s) = 0) then PCPC+k + 1 if (Z = 1) then PC PC + k + 1 if (Z = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 0) then PC PC + k + 1 if (C = 1) then PC PC + k + 1 if (N = 1) then PC PC + k + 1 if (N = 0) then PC PC + k + 1 if (N V= 0) then PC PC + k + 1 if (N V= 1) then PC PC + k + 1 if (H = 1) then PC PC + k + 1 if (H = 0) then PC PC + k + 1 if (T = 1) then PC PC + k + 1 if (T = 0) then PC PC + k + 1 if (V = 1) then PC PC + k + 1 if (V = 0) then PC PC + k + 1 if ( I = 1) then PC PC + k + 1 if ( I = 0) then PC PC + k + 1
Flags
Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,H Z,C,N,V,S Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,C,N,V Z,C,N,V,H Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V Z,N,V None None None None None None I None Z, N,V,C,H Z, N,V,C,H Z, N,V,C,H None None None None None None None None None None None None None None None None None None None None None None None None
#Clocks
1 1 2 1 1 1 1 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 3 3 4 4 1/2 1 1 1 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2 1/2
ARITHMETIC AND LOGIC INSTRUCTIONS ADD Rd, Rr Add two Registers ADC Rd, Rr Add with Carry two Registers ADIW Rdl,K Add Immediate to Word SUB Rd, Rr Subtract two Registers SUBI Rd, K Subtract Constant from Register SBC Rd, Rr Subtract with Carry two Registers SBCI Rd, K Subtract with Carry Constant from Reg. SBIW Rdl,K Subtract Immediate from Word AND Rd, Rr Logical AND Registers ANDI Rd, K Logical AND Register and Constant OR Rd, Rr Logical OR Registers ORI Rd, K Logical OR Register and Constant EOR Rd, Rr Exclusive OR Registers COM Rd One's Complement NEG Rd Two's Complement SBR Rd,K Set Bit(s) in Register CBR Rd,K Clear Bit(s) in Register INC Rd Increment DEC Rd Decrement TST Rd Test for Zero or Minus CLR Rd Clear Register SER Rd Set Register BRANCH INSTRUCTIONS RJMP k Relative Jump IJMP Indirect Jump to (Z) RCALL k Relative Subroutine Call ICALL Indirect Call to (Z) RET Subroutine Return RETI Interrupt Return CPSE Rd,Rr Compare, Skip if Equal CP Rd,Rr Compare CPC Rd,Rr Compare with Carry CPI Rd,K Compare Register with Immediate SBRC Rr, b Skip if Bit in Register Cleared SBRS Rr, b Skip if Bit in Register is Set SBIC P, b Skip if Bit in I/O Register Cleared SBIS P, b Skip if Bit in I/O Register is Set BRBS s, k Branch if Status Flag Set BRBC s, k Branch if Status Flag Cleared BREQ k Branch if Equal BRNE k Branch if Not Equal BRCS k Branch if Carry Set BRCC k Branch if Carry Cleared BRSH k Branch if Same or Higher BRLO k Branch if Lower BRMI k Branch if Minus BRPL k Branch if Plus BRGE k Branch if Greater or Equal, Signed BRLT k Branch if Less Than Zero, Signed BRHS k Branch if Half Carry Flag Set BRHC k Branch if Half Carry Flag Cleared BRTS k Branch if T Flag Set BRTC k Branch if T Flag Cleared BRVS k Branch if Overflow Flag is Set BRVC k Branch if Overflow Flag is Cleared BRIE k Branch if Interrupt Enabled BRID k Branch if Interrupt Disabled
7
Mnemonics
Operands
Description
Move Between Registers Load Immediate Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Indirect Load Indirect and Post-Inc. Load Indirect and Pre-Dec. Load Indirect with Displacement Load Direct from SRAM Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Indirect Store Indirect and Post-Inc. Store Indirect and Pre-Dec. Store Indirect with Displacement Store Direct to SRAM Load Program Memory In Port Out Port Push Register on Stack Pop Register from Stack Set Bit in I/O Register Clear Bit in I/O Register Logical Shift Left Logical Shift Right Rotate Left Through Carry Rotate Right Through Carry Arithmetic Shift Right Swap Nibbles Flag Set Flag Clear Bit Store from Register to T Bit load from T to Register Set Carry Clear Carry Set Negative Flag Clear Negative Flag Set Zero Flag Clear Zero Flag Global Interrupt Enable Global Interrupt Disable Set Signed Test Flag Clear Signed Test Flag Set Twos Complement Overflow. Clear Twos Complement Overflow Set T in SREG Clear T in SREG Set Half Carry Flag in SREG Clear Half Carry Flag in SREG No Operation Sleep Watchdog Reset
Operation
Rd Rr Rd K Rd (X) Rd (X), X X + 1 X X - 1, Rd (X) Rd (Y) Rd (Y), Y Y + 1 Y Y - 1, Rd (Y) Rd (Y + q) Rd (Z) Rd (Z), Z Z+1 Z Z - 1, Rd (Z) Rd (Z + q) Rd (k) (X) Rr (X) Rr, X X + 1 X X - 1, (X) Rr (Y) Rr (Y) Rr, Y Y + 1 Y Y - 1, (Y) Rr (Y + q) Rr (Z) Rr (Z) Rr, Z Z + 1 Z Z - 1, (Z) Rr (Z + q) Rr (k) Rr R0 (Z) Rd P P Rr STACK Rr Rd STACK I/O(P,b) 1 I/O(P,b) 0 Rd(n+1) Rd(n), Rd(0) 0 Rd(n) Rd(n+1), Rd(7) 0 Rd(0)C,Rd(n+1) Rd(n),CRd(7) Rd(7)C,Rd(n) Rd(n+1),CRd(0) Rd(n) Rd(n+1), n=0..6 Rd(3..0)Rd(7..4),Rd(7..4)Rd(3..0) SREG(s) 1 SREG(s) 0 T Rr(b) Rd(b) T C1 C0 N1 N0 Z1 Z0 I1 I0 S1 S0 V1 V0 T1 T0 H1 H0 (see specific descr. for Sleep function) (see specific descr. for WDR/timer)
Flags
None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None None Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V Z,C,N,V None SREG(s) SREG(s) T None C C N N Z Z I I S S V V T T H H None None None
#Clocks
1 1 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 3 1 1 2 2 2 2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1
DATA TRANSFER INSTRUCTIONS MOV Rd, Rr LDI Rd, K LD Rd, X LD Rd, X+ LD Rd, - X LD Rd, Y LD Rd, Y+ LD Rd, - Y LDD Rd,Y+q LD Rd, Z LD Rd, Z+ LD Rd, -Z LDD Rd, Z+q LDS Rd, k ST X, Rr ST X+, Rr ST - X, Rr ST Y, Rr ST Y+, Rr ST - Y, Rr STD Y+q,Rr ST Z, Rr ST Z+, Rr ST -Z, Rr STD Z+q,Rr STS k, Rr LPM IN Rd, P OUT P, Rr PUSH Rr POP Rd BIT AND BIT-TEST INSTRUCTIONS SBI P,b CBI P,b LSL Rd LSR Rd ROL Rd ROR Rd ASR Rd SWAP Rd BSET s BCLR s BST Rr, b BLD Rd, b SEC CLC SEN CLN SEZ CLZ SEI CLI SES CLS SEV CLV SET CLT SEH CLH NOP SLEEP WDR
8
AT90S/LS4434 and AT90S/LS8535
AT90S/LS4434 and AT90S/LS8535
Ordering Information
Power Supply 2.7 - 6.0V Speed (MHz) 4 Ordering Code AT90LS4434-4AC AT90LS4434-4JC AT90LS4434-4PC AT90LS4434-4AI AT90LS4434-4JI AT90LS4434-4PI 4.0 - 6.0V 8 AT90S4434-8AC AT90S4434-8JC AT90S4434-8JC AT90S4434-8AI AT90S4434-8JI AT90S4434-8PI 2.7 - 6.0V 4 AT90LS8535-4AC AT90LS8535-4JC AT90LS8535-4PC AT90LS8535-4AI AT90LS8535-4JI AT90LS8535-4PI 4.0 - 6.0V 8 AT90S8535-8AC AT90S8535-8JC AT90S8535-8JC AT90S8535-8AI AT90S8535-8JI AT90S8535-8PI Package 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 44A 44J 40P6 Operation Range Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C) Commercial (0°C to 70°C) Industrial (-40°C to 85°C)
Package Type
44A 44J 40P6
44 Lead, Thin (1.0mm) Plastic Gull Wing Quad Flat Package (TQFP) 44 Lead, Plastic J-Leaded Chip Carrier (PLCC) 40 Lead, 0.600" Wide, Plastic Dual in Line Package (PDIP)
9
Packaging Information
44A, 44-Lead, Thin (1.0 mm) Plastic Gull Wing Quad Flat Package (TQFP) Dimensions in Millimeters and (Inches) 44J, 44-Lead, Plastic J-Leaded Chip Carrier (PLCC) Dimensions in Inches and (Millimeters)
.045(1.14) X 45°
PIN NO. 1 IDENTIFY
.045(1.14) X 30° - 45°
.012(.305) .008(.203)
.656(16.7) SQ .650(16.5) .032(.813) .026(.660) .695(17.7) SQ .685(17.4)
.630(16.0) .590(15.0) .021(.533) .013(.330)
.050(1.27) TYP .500(12.7) REF SQ
.043(1.09) .020(.508) .120(3.05) .090(2.29) .180(4.57) .165(4.19)
.022(.559) X 45° MAX (3X)
*Controlling dimension: millimeters
40P6, 40-Lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-011 AC
2.07(52.6) 2.04(51.8)
PIN 1
.566(14.4) .530(13.5)
1.900(48.26) REF .220(5.59) MAX SEATING PLANE .161(4.09) .125(3.18) .110(2.79) .090(2.29) .065(1.65) .041(1.04) .630(16.0) .590(15.0) 0 REF 15 .690(17.5) .610(15.5)
.090(2.29) MAX .005(.127) MIN
.065(1.65) .015(.381) .022(.559) .014(.356)
.012(.305) .008(.203)
10
AT90S/LS4434 and AT90S/LS8535