Atmel AT90S4434 free download

File name 90S8535.PDF

Features · · · · Utilizes the AVR ® Enhanced RISC Architecture AVR - High Performance and Low Power RISC Architecture 118 Powerful Instructions - Most Single Clock Cycle Execution 8K bytes of In-System Programmable Flash AT90S/LS8535 4K bytes of In-System Programmable Flash AT90S/LS4434 ­ SPI Serial Interface for In-System Programming ­ Endurance: 1,000 Write/Erase Cycles 512 bytes EEPROM AT90S/LS8535 256 bytes EEPROM AT90S/LS4434 ­ Endurance: 100,000 Write/Erase Cycles 512 bytes Internal SRAM AT90S/LS8535 256 bytes Internal SRAM AT90S/LS4434 8-Channel, 10-Bit ADC 32 x 8 General Purpose Working Registers 32 Programmable I/O Lines Programmable Serial UART VCC: 4.0 - 6.0V AT90S4434/AT90S8535 VCC: 2.7 - 6.0V AT90LS4434/AT90LS8535 Speed Grades: 0 - 8 MHz AT90S4434/AT90S8535, 0 - 4 MHz (AT90LS4434/AT90LS8535 Power-On Reset Circuit Up to 8 MIPS Throughput at 8 MHz RTC with Separate Oscillator and Counter Mode Two 8-Bit Timer/Counters with Separate Prescaler and Compare Mode One 16-Bit Timer/Counter with Separate Prescaler and Compare and Capture Modes 3 PWM channels External and Internal Interrupt Sources Programmable Watchdog Timer with On-Chip Oscillator On-Chip Analog Comparator Three Sleep Modes: Idle, Power Save, and Power Down Programming Lock for Software Security · · · · · · · · · · · · · · · · · · · · 8-Bit Microcontroller with 4K/8K Bytes In-System Programmable Flash AT90S4434 AT90LS4434 AT90S8535 AT90LS8535 Advance Information Description The AT90S4434/8535 is a low-power CMOS 8-bit microcontroller based on the AVR® enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the AT90S4434/8535 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize power consumption versus processing speed. (continued) Pin Configurations Rev. 1041AS­05/98 Note: This is a summary document. For the complete 80 page document, please visit our website at www.atmel.com or e-mail at 1 [email protected] and request literature #1041A. Block Diagram PA0 - PA7 PC0 - PC7 VCC PORTA DRIVERS PORTC DRIVERS GND DATA REGISTER PORTA DATA DIR. REG. PORTA DATA REGISTER PORTC DATA DIR. REG. PORTC 8-BIT DATA BUS AVCC ANALOG MUX AGND AREF ADC OSCILLATOR XTAL1 INTERNAL OSCILLATOR OSCILLATOR PROGRAM COUNTER STACK POINTER WATCHDOG TIMER TIMING AND CONTROL XTAL2 RESET PROGRAM FLASH SRAM MCU CONTROL REGISTER INSTRUCTION REGISTER GENERAL PURPOSE REGISTERS X Y Z TIMER/ COUNTERS INSTRUCTION DECODER INTERRUPT UNIT CONTROL LINES ALU EEPROM STATUS REGISTER PROGRAMMING LOGIC SPI UART ANALOG COMPARATOR DATA REGISTER PORTB DATA DIR. REG. PORTB DATA REGISTER PORTD DATA DIR. REG. PORTD + - PORTB DRIVERS PORTD DRIVERS PB0 - PB7 PD0 - PD7 The AVR core combines a rich instruction set with 32 general purpose working registers. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be accessed in one single instruction executed in