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Schematic Diagram



7. Schematic Diagram
7-1 Circuit Description
Logic Board Y Main Board X Main Board


Display Row PDP Panel
DRAM Data Driver 42" - 1024x768 Pixels
Input 1024x768x3 Cells (R,G,B) X-Pulse
Data 50" - 1360x768 Pixels
Data Display Generator
Controller Driver 1360x768x3 Cells (R,G,B)
Processor Timing Y-Pulse
Timing
Controller Generator
Scan
Timing
Address Buffer

SMPS Board


LVDS
Main SMPS


Main Board

LVDS Image Audio
Deinterlacer
Trans Enhancer Processor

Image CPU Video Speaker
Decoder Decoder Out
AC Power
Scaler RF
Tuner Source
Splitter
TMDS A/D Video
Converter S/W Micom
Recever


SMPS Board
The SMPS used for the PDP has been designed to be efficient, compact and lightweight. For VS and VA outputs, a LLC converter
has been used. For the other outputs, a Flyback converter has been used.

LOGIC Board
The logic circuit consists of a Logic Main Board and an Address Buffer Board. The Logic Main Board decodes the video signal
encoded by the Video Board, outputs the ADDRESS data signal for each pattern and generates X and Y drive signals. The
Address Buffer Board buffers and transfers the ADDRESS data output signal using TCP IC.
- LVDS with built-in video signal processing (W/L, error diffusion, APC, FCR, etc.) applied and 1 ASIC chip.
- Outputs the address Drive IC control and data signals to the Buffer Board.
- Outputs the control signal for the X and Y Drive Boards.
- Monitors major drive voltages (Micom Circuit Block); detects if a surge voltage has been applied and protects the Drive Circuit.
- Temperature Adaptive Operating Mode (Low Temperature/Room Temperature/High Temperature); Discharge optimization for
each temperature level.

X-MAIN Board
Connects to the X terminal block, 1) provides maintaining voltage waveform (including ERC), and 2) maintains the Ve bias in the
Scan section.

Y-MAIN Board
Connects to the Y terminal block, 1) provides maintaining voltage waveform (including ERC), 2) provides Y Rising, Falling Ramp
waveforms, and 3) maintains the Vscan bias.

Address Buffer Board
It delivers the data signal and control signal to the TCP.

Samsung Electronics 7-1
MEMO




7-2 Samsung Electronics
Schematic Diagram


7-2 Schematic Diagram
7-2-1 POWER_ETC
This Document can not be used without Samsung's authorization.



Function
Power B12V B9V


Vidoe IC101
BA178M09FP TP101




P OWE R
1 3 1
IN OUT


Audio G ND

2
C105
100uF
16V


C104 C101 C102 C103
100uF 100nF 10nF 100nF
16V PGND VCC_PANEL XREF
A5V_1 B5V_VCCA BD111
CIC21J601NE XREF
IR
IC102_CPT IC103 KEY_INPUT1
XREF
G78D12AT45U TP119 FDS9933A A5V A5V_1 KEY_INPUT2

1
IN OUT
3 1 1 8 A5V
2 7 Q101_DE
D109 KSC1623-Y TP126
GND 3 6 PMLL4148
C109 R157
C107_CPT 4 5 1




C


E
2 0ohm 1.5Kohm
22uF 22uF C106
16V




B
16V 100nF C110 C114
R101_DE




MMBD4148SE




MMBD4148SE




MMBD4148SE
R102 1uF




2

1



2

1



2

1
100nF
TP133 100Kohm 10V C 111




3
C112




D101




D102




D103
24
C108_CPT 22uF 100nF
23 1 220ohm 16V
100nF R130




2
22 1/10W B1.8VD C113_DE
R105 R106 R107




3




3




3




1
21 R103 47Kohm D104_DE
PGND PGND 100nF R108
20 10Kohm BZX84C5V6LT1
TP134 4.7Kohm
BD110 C
1




19 1/10W B XR EF LED_RED
CIC21J601NE
18 STB_SW E
17 XREF Q103
TP135 2SC2412K-Q
1




16 BD108
15 BD101_OP
CN102
1 B A
A5V_1
STB1.8A R131 SMAW200-10P(P)




U101
14 1/10W
2 1




-
13 B A 4.7Kohm
TP136
1




12 1 BD104
C
2 TP141 A B




1
11 TP106
B12VS (PDP:18V) B5V B5V_VCCA Q102
B SW_PVCC R154_DE B5V_VCCA




1
10 XREF 3 R155 100ohm
BD105 E
2SC2412K-Q R104 TP109 4.7Kohm




1
9 CIC21J601NE 4 1/10W
TP108 10Kohm PGND
1




1 1
8 5 TP128 R142 XREF BUZZER
1




7 T P 12 0 6 TP129 1Kohm
R133
1




6 TP110 4.7Kohm 7 R156 100ohm XREF DEFAULT_NET_TYPE
DIR_BUZZER
PGND




1
5 8 1/10W




TP105
1/10W TP130 R153_DE
4 C119_L C120 9 1 R146
33ohm 1Kohm
3 22uF 100uF