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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document by MMDF3N03HD/D
Designer's
TM Data Sheet
Medium Power Surface Mount Products
MMDF3N03HD
Motorola Preferred Device
TMOS Dual N-Channel Field Effect Transistors
MiniMOSTM devices are an advanced series of power MOSFETs which utilize Motorola's High Cell Density HDTMOS process. These miniature surface mount MOSFETs feature ultra low RDS(on) and true logic level performance. They are capable of withstanding high energy in the avalanche and commutation modes and the draintosource diode has a very low reverse recovery time. MiniMOS devices are designed for use in low voltage, high speed switching applications where power efficiency is important. Typical applications are dcdc converters, and power management in portable and battery powered products such as computers, printers, cellular and cordless phones. They can also be used for low voltage motor controls in mass storage products such as disk drives and tape drives. The avalanche energy is specified to eliminate the guesswork in designs where inductive loads are switched and offer additional safety margin against unexpected voltage transients. · · · · · · · ·
TM
DUAL TMOS POWER MOSFET 4.1 AMPERES 30 VOLTS RDS(on) = 0.070 OHM
D
G S
CASE 75105, Style 11 SO8
Ultra Low RDS(on) Provides Higher Efficiency and Extends Battery Life Logic Level Gate Drive -- Can Be Driven by Logic ICs Miniature SO8 Surface Mount Package -- Saves Board Space Diode Is Characterized for Use In Bridge Circuits Diode Exhibits High Speed, With Soft Recovery IDSS Specified at Elevated Temperature Avalanche Energy Specified Mounting Information for SO8 Package Provided
Source1 Gate1 Source2 Gate2
1 2 3 4
8 7 6 5
Drain1 Drain1 Drain2 Drain2
Top View
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating DraintoSource Voltage DraintoGate Voltage (RGS = 1.0 M) GatetoSource Voltage -- Continuous Drain Current -- Continuous @ TA = 25°C Drain Current -- Continuous @ TA = 100°C Drain Current -- Single Pulse (tp 10 µs) Total Power Dissipation @ TA = 25°C (1) Operating and Storage Temperature Range Single Pulse DraintoSource Avalanche Energy -- Starting TJ = 25°C (VDD = 30 Vdc, VGS = 5.0 Vdc, Peak IL = 9.0 Apk, L = 8.0 mH, RG = 25 ) Thermal Resistance -- Junction to Ambient (1) Maximum Lead Temperature for Soldering Purposes, 1/8 from case for 10 seconds Symbol VDSS VDGR VGS ID ID IDM PD TJ, Tstg EAS RJA TL Value 30 30 ± 20 4.1 3.0 40 2.0 55 to 150 324 62.5 260 Unit Vdc Vdc Vdc Adc Apk Watts °C mJ °C/W °C
DEVICE MARKING
D3N03
ORDERING INFORMATION
Device Reel Size Tape Width Quantity MMDF3N03HDR2 13 12 mm embossed tape 2500 units (1) When mounted on 2" square FR4 board (1" square 2 oz. Cu 0.06" thick single sided) with one die operating, 10s max.
Designer's Data for "Worst Case" Conditions -- The Designer's Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit curves -- representing boundaries on device characteristics -- are given to facilitate "worst case" design.
Designer's, HDTMOS and MiniMOS are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value. REV 6
©Motorola TMOS Power MOSFET Transistor Device Data Motorola, Inc. 1996
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MMDF3N03HD
ELECTRICAL CHARACTERISTICS (TA = 25°C unless otherwise noted)
Characteristic OFF CHARACTERISTICS DraintoSource Breakdown Voltage (VGS = 0 Vdc, ID = 250 µAdc) Temperature Coefficient (Positive) Zero Gate Voltage Drain Current (VDS = 30 Vdc, VGS = 0 Vdc) (VDS = 30 Vdc, VGS = 0 Vdc, TJ = 125°C) GateBody Leakage Current (VGS = ± 20 Vdc, VDS = 0) ON CHARACTERISTICS(1) Gate Threshold Voltage (VDS = VGS, ID = 250 µAdc) Threshold Temperature Coefficient (Negative) Static DraintoSource OnResistance (VGS = 10 Vdc, ID = 3.0 Adc) (VGS = 4.5 Vdc, ID = 1.5 Adc) Forward Transconductance (VDS = 3.0 Vdc, ID = 1.5 Adc) DYNAMIC CHARACTERISTICS Input Capacitance Output Capacitance Transfer Capacitance SWITCHING CHARACTERISTICS(2) TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time TurnOn Delay Time Rise Time TurnOff Delay Time Fall Time Gate Charge (VDS = 10 Vdc, ID = 3.0 Adc, VGS = 10 Vdc) (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 10 Vdc, RG = 9.1 ) (VDD = 15 Vdc, ID = 3.0 Adc, VGS = 4.5 Vdc, RG = 9.1 ) td(on) tr td(off) tf td(on) tr td(off) tf QT Q1 Q2 Q3 SOURCEDRAIN DIODE CHARACTERISTICS Forward OnVoltage(1) (IS = 3.0 Adc, VGS = 0 Vdc) (IS = 3.0 Adc, VGS = 0 Vdc, TJ = 125°C) Reverse Recovery Time See Figure 12 -- -- -- -- -- -- -- -- -- -- -- -- 12 65 16 19 8 15 30 23 11.5 1.5 3.5 2.8 24 130 32 38 16 30 60 46 16 -- -- -- nC ns ns (VDS = 24 Vdc, VGS = 0 Vdc, f = 1.0 MHz) Ciss Coss Crss -- -- -- 450 160 35 630 225 70 pF VGS(th) 1.0 RDS(on) -- -- gFS 2.0 3.6 -- 0.06 0.065 0.07 0.075 Mhos 1.7 3.0 mV/°C Ohms Vdc V(BR)DSS 30 -- IDSS -- -- IGSS -- -- -- -- 1.0 10 100 nAdc -- 34.5 -- -- Vdc mV/°C µAdc Symbol Min Typ Max Unit
VSD -- -- trr -- -- -- -- 0.82 0.7 24 17 7 0.025 1.2 -- -- -- -- --
Vdc
ns
(IS = 3.0 Adc, VGS = 0 Vdc, dIS/dt = 100 A/µs)
ta tb
Reverse Recovery Storage Charge (1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%. (2) Switching characteristics are independent of operating junction temperature.
QRR
µC
2
Motorola TMOS Power MOSFET Transistor Device Data
MMDF3N03HD
TYPICAL ELECTRICAL CHARACTERISTICS
6 I D , DRAIN CURRENT (AMPS) VGS = 10 V 4.5 V 5 4.3 V 4.1 V 4 3 2 2.9 V 1 0 2.7 V 2.5 V 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2 3.9 V 3.7 V 3.3 V 3.5 V 6 TJ = 25°C I D , DRAIN CURRENT (AMPS) 5 4 100°C 3 2 1 0 25°C TJ = 55°C VDS 10 V
3.1 V
2
2.5
3
3.5
4
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
VGS, GATETOSOURCE VOLTAGE (VOLTS)
Figure 1. OnRegion Characteristics
RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS) RDS(on) , DRAINTOSOURCE RESISTANCE (OHMS)
Figure 2. Transfer Characteristics
0.6 0.5 0.4 0.3 0.2 0.1 0 2 3 4 5 6 7 8 9 VGS, GATETOSOURCE VOLTAGE (VOLTS) 10 ID = 1.5 A TJ = 25°C
0.08 TJ = 25°C
0.07 VGS = 4.5
0.06 10 V
0.05 0 0.5 1 1.5 2 2.5 3 ID, DRAIN CURRENT (AMPS)
Figure 3. OnResistance versus GatetoSource Voltage
RDS(on), DRAINTOSOURCE RESISTANCE (NORMALIZED)
Figure 4. OnResistance versus Drain Current and Gate Voltage
2.0 VGS = 10 V ID = 1.5 A I DSS , LEAKAGE (nA) 1.5
100 VGS = 0 V TJ = 125°C
1.0
10
100°C
0.5
0 50
25
0
25
50
75
100
125
150
1
0
5
10
15
20
25
30
TJ, JUNCTION TEMPERATURE (°C)
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
Figure 5. OnResistance Variation with Temperature
Figure 6. DraintoSource Leakage Current versus Voltage
Motorola TMOS Power MOSFET Transistor Device Data
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MMDF3N03HD
POWER MOSFET SWITCHING
Switching behavior is most easily modeled and predicted by recognizing that the power MOSFET is charge controlled. The lengths of various switching intervals (t) are determined by how fast the FET input capacitance can be charged by current from the generator. The published capacitance data is difficult to use for calculating rise and fall because draingate capacitance varies greatly with applied voltage. Accordingly, gate charge data is used. In most cases, a satisfactory estimate of average input current (IG(AV)) can be made from a rudimentary analysis of the drive circuit so that t = Q/IG(AV) During the rise and fall time interval when switching a resistive load, VGS remains virtually constant at a level known as the plateau voltage, VSGP. Therefore, rise and fall times may be approximated by the following: tr = Q2 x RG/(VGG VGSP) tf = Q2 x RG/VGSP where VGG = the gate drive voltage, which varies from zero to VGG RG = the gate drive resistance and Q2 and VGSP are read from the gate charge curve. The switching characteristics of a MOSFET body diode are very important in systems using it as a freewheeling or commutating diode. Of particular interest are the reverse recovery characteristics which play a major role in determining switching losses, radiated noise, EMI and RFI. System switching losses are largely due to the nature of the body diode itself. The body diode is a minority carrier device, therefore it has a finite reverse recovery time, trr, due to the storage of minority carrier charge, QRR, as shown in the typical reverse recovery wave form of Figure 11. It is this stored charge that, when cleared from the diode, passes through a potential and defines an energy loss. Obviously, repeatedly forcing the diode through reverse recovery further increases switching losses. Therefore, one would like a diode with short t rr and low QRR specifications to minimize these losses. The abruptness of diode reverse recovery effects the amount of radiated noise, voltage spikes, and current ringing. The mechanisms at work are finite irremovable circuit parasitic inductances and capacitances acted upon by high
di/dt = 300 A/µs I S , SOURCE CURRENT
During the turnon and turnoff delay times, gate current is not constant. The simplest calculation uses appropriate values from the capacitance curves in a standard equation for voltage change in an RC network. The equations are: td(on) = RG Ciss In [VGG/(VGG VGSP)] td(off) = RG Ciss In (VGG/VGSP) The capacitance (Ciss) is read from the capacitance curve at a voltage corresponding to the offstate condition when calculating td(on) and is read at a voltage corresponding to the onstate when calculating td(off). At high switching speeds, parasitic circuit elements complicate the analysis. The inductance of the MOSFET source lead, inside the package and in the circuit wiring which is common to both the drain and gate current paths, produces a voltage at the source which reduces the gate drive current. The voltage is determined by Ldi/dt, but since di/dt is a function of drain current, the mathematical solution is complex. The MOSFET output capacitance also complicates the mathematics. And finally, MOSFETs have finite internal gate resistance which effectively adds to the resistance of the driving source, but the internal resistance is difficult to measure and, consequently, is not specified. di/dts. The diode's negative di/dt during ta is directly controlled by the device clearing the stored charge. However, the positive di/dt during tb is an uncontrollable diode characteristic and is usually the culprit that induces current ringing. Therefore, when comparing diodes, the ratio of tb/ta serves as a good indicator of recovery abruptness and thus gives a comparative estimate of probable noise generated. A ratio of 1 is considered ideal and values less than 0.5 are considered snappy. Compared to Motorola standard cell density low voltage MOSFETs, high cell density MOSFET diodes are faster (shorter trr), have less stored charge and a softer reverse recovery characteristic. The softness advantage of the high cell density diode means they can be forced through reverse recovery at a higher di/dt than a standard cell MOSFET diode without increasing the current ringing or the noise generated. In addition, power dissipation incurred from switching the diode will be less due to the shorter recovery time and lower switching losses.
Standard Cell Density trr High Cell Density trr tb ta
DRAINTOSOURCE DIODE CHARACTERISTICS
t, TIME
Figure 7. Reverse Recovery Time (trr) 4 Motorola TMOS Power MOSFET Transistor Device Data
MMDF3N03HD
SAFE OPERATING AREA
The Forward Biased Safe Operating Area curves define the maximum simultaneous draintosource voltage and drain current that a transistor can handle safely when it is forward biased. Curves are based upon maximum peak junction temperature and a case temperature (TC) of 25°C. Peak repetitive pulsed power limits are determined by using the thermal response data in conjunction with the procedures discussed in AN569, "Transient Thermal Resistance General Data and Its Use." Switching between the offstate and the onstate may traverse any load line provided neither rated peak current (IDM) nor rated voltage (VDSS) is exceeded, and that the transition time (tr, tf) does not exceed 10 µs. In addition the total power averaged over a complete switching cycle must not exceed (TJ(MAX) TC)/(RJC). A power MOSFET designated EFET can be safely used in switching circuits with unclamped inductive loads. For reliable operation, the stored energy from circuit inductance dissipated in the transistor while in avalanche must be less than the rated limit and must be adjusted for operating conditions differing from those specified. Although industry practice is to rate in terms of energy, avalanche energy capability is not a constant. The energy rating decreases nonlinearly with an increase of peak current in avalanche and peak junction temperature. Although many EFETs can withstand the stress of drain tosource avalanche at currents up to rated pulsed current (IDM), the energy rating is specified at rated continuous current (ID), in accordance with industry custom. The energy rating must be derated for temperature as shown in the accompanying graph (Figure 9). Maximum energy at currents below rated continuous ID can safely be assumed to equal the values indicated.
TJ = 25°C
VGS, GATETOSOURCE VOLTAGE (VOLTS)
1200 1000 C, CAPACITANCE (pF) 800 600 400 200 0 10
VDS = 0 V VGS = 0 V Ciss
12 QT 9 VDS 6 Q1 Q2
24
VGS
18
Crss
12
Ciss
Coss Crss 5 5 30 0 10 15 20 25 VGS VDS GATETOSOURCE OR DRAINTOSOURCE VOLTAGE (VOLTS)
3 Q3 0 ID = 3 A TJ = 25°C 2 4 6 8 Qg, TOTAL GATE CHARGE (nC) 10
6
0
0 12
Figure 8. Capacitance Variation
Figure 9. GatetoSource and DraintoSource Voltage versus Total Charge
3.0 TJ = 25°C VGS = 0 V
1000 VDD = 15 V ID = 3 A VGS = 10 V TJ = 25°C
2.5 IS, SOURCE CURRENT (AMPS) 2.0 1.5 1.0 0.5 0 0.5
100 t, TIME (ns)
10
td(off) tr tf td(on)
1
1
10 RG, GATE RESISTANCE (OHMS)
100
0.6 0.65 0.7 0.75 0.8 0.55 VSD, SOURCETODRAIN VOLTAGE (VOLTS)
0.85
Figure 10. Resistive Switching Time Variation versus Gate Resistance
Figure 11. Diode Forward Voltage versus Current
Motorola TMOS Power MOSFET Transistor Device Data
5
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
MMDF3N03HD
100 I D , DRAIN CURRENT (AMPS) 10 µs 100 µs 1 ms 10 ms 1 dc RDS(on) LIMIT THERMAL LIMIT PACKAGE LIMIT
Mounted on 2" sq. FR4 board (1" sq. 2 oz. Cu 0.06" thick single sided) with one die operating, 10s max.
350 EAS, SINGLE PULSE DRAIN-TO-SOURCE AVALANCHE ENERGY (mJ) VGS = 20 V SINGLE PULSE TC = 25°C ID = 9 A 300 250 200 150 100 50 0 25 50 75 100 125 150
10
0.1
0.01 0.1
1
10
100
VDS, DRAINTOSOURCE VOLTAGE (VOLTS)
TJ, STARTING JUNCTION TEMPERATURE (°C)
Figure 12. Maximum Rated Forward Biased Safe Operating Area
Figure 13. Maximum Avalanche Energy versus Starting Junction Temperature
TYPICAL ELECTRICAL CHARACTERISTICS
10 Rthja(t), EFFECTIVE TRANSIENT THERMAL RESISTANCE
1
D = 0.5 0.2 0.1 0.05 0.02 0.01
0.1
Normalized to ja at 10s.
Chip
0.0175 0.0710 0.2706 0.5776 0.7086
0.01 SINGLE PULSE 0.001 1.0E05 1.0E04 1.0E03 1.0E02
0.0154 F 0.0854 F 0.3074 F 1.7891 F 107.55 F
Ambient 1.0E+03
1.0E01 t, TIME (s)
1.0E+00
1.0E+01
1.0E+02
Figure 14. Thermal Response
di/dt IS trr ta tb TIME tp IS 0.25 IS
Figure 15. Diode Reverse Recovery Waveform
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Motorola TMOS Power MOSFET Transistor Device Data
MMDF3N03HD
INFORMATION FOR USING THE SO8 SURFACE MOUNT PACKAGE
MINIMUM RECOMMENDED FOOTPRINT FOR SURFACE MOUNTED APPLICATIONS
Surface mount board layout is a critical portion of the total design. The footprint for the semiconductor packages must be the correct size to ensure proper solder connection interface between the board and the package. With the correct pad geometry, the packages will selfalign when subjected to a solder reflow process.
0.060 1.52
0.275 7.0
0.155 4.0
0.024 0.6
0.050 1.270
inches mm
SO8 POWER DISSIPATION
The power dissipation of the SO8 is a function of the input pad size. This can vary from the minimum pad size for soldering to the pad size given for maximum power dissipation. Power dissipation for a surface mount device is determined by TJ(max), the maximum rated junction temperature of the die, RJA, the thermal resistance from the device junction to ambient; and the operating temperature, TA. Using the values provided on the data sheet for the SO8 package, PD can be calculated as follows: PD = TJ(max) TA RJA the equation for an ambient temperature TA of 25°C, one can calculate the power dissipation of the device which in this case is 2.0 Watts. PD = 150°C 25°C = 2.0 Watts 62.5°C/W The 62.5°C/W for the SO8 package assumes the recommended footprint on a glass epoxy printed circuit board to achieve a power dissipation of 2.0 Watts using the footprint shown. Another alternative would be to use a ceramic substrate or an aluminum core board such as Thermal CladTM. Using board material such as Thermal Clad, the power dissipation can be doubled using the same footprint.
The values for the equation are found in the maximum ratings table on the data sheet. Substituting these values into
SOLDERING PRECAUTIONS
The melting temperature of solder is higher than the rated temperature of the device. When the entire device is heated to a high temperature, failure to complete soldering within a short time could result in device failure. Therefore, the following items should always be observed in order to minimize the thermal stress to which the devices are subjected. · Always preheat the device. · The delta temperature between the preheat and soldering should be 100°C or less.* · When preheating and soldering, the temperature of the leads and the case must not exceed the maximum temperature ratings as shown on the data sheet. When using infrared heating with the reflow soldering method, the difference shall be a maximum of 10°C.
· The soldering temperature and time shall not exceed · When shifting from preheating to soldering, the maximum · After soldering has been completed, the device should be
allowed to cool naturally for at least three minutes. Gradual cooling should be used as the use of forced cooling will increase the temperature gradient and result in latent failure due to mechanical stress. · Mechanical stress or shock should not be applied during cooling. * Soldering a device without preheating can cause excessive thermal shock and stress which can result in damage to the device. temperature gradient shall be 5°C or less. 260°C for more than 10 seconds.
Motorola TMOS Power MOSFET Transistor Device Data
7
MMDF3N03HD
TYPICAL SOLDER HEATING PROFILE
For any given circuit board, there will be a group of control settings that will give the desired heat pattern. The operator must set temperatures for several heating zones and a figure for belt speed. Taken together, these control settings make up a heating "profile" for that particular circuit board. On machines controlled by a computer, the computer remembers these profiles from one operating session to the next. Figure 12 shows a typical heating profile for use when soldering a surface mount device to a printed circuit board. This profile will vary among soldering systems, but it is a good starting point. Factors that can affect the profile include the type of soldering system in use, density and types of components on the board, type of solder used, and the type of board or substrate material being used. This profile shows temperature versus time. The line on the graph shows the actual temperature that might be experienced on the surface of a test board at or near a central solder joint. The two profiles are based on a high density and a low density board. The Vitronics SMD310 convection/infrared reflow soldering system was used to generate this profile. The type of solder used was 62/36/2 Tin Lead Silver with a melting point between 177 189°C. When this type of furnace is used for solder reflow work, the circuit boards and solder joints tend to heat first. The components on the board are then heated by conduction. The circuit board, because it has a large surface area, absorbs the thermal energy more efficiently, then distributes this energy to the components. Because of this effect, the main body of a component may be up to 30 degrees cooler than the adjacent solder joints.
STEP 1 PREHEAT ZONE 1 "RAMP" 200°C
STEP 2 STEP 3 VENT HEATING "SOAK" ZONES 2 & 5 "RAMP"
DESIRED CURVE FOR HIGH MASS ASSEMBLIES 150°C
STEP 5 STEP 4 HEATING HEATING ZONES 3 & 6 ZONES 4 & 7 "SPIKE" "SOAK" 170°C 160°C
STEP 6 VENT
STEP 7 COOLING 205° TO 219°C PEAK AT SOLDER JOINT
150°C SOLDER IS LIQUID FOR 40 TO 80 SECONDS (DEPENDING ON MASS OF ASSEMBLY)
100°C 100°C
140°C
DESIRED CURVE FOR LOW MASS ASSEMBLIES 50°C
TIME (3 TO 7 MINUTES TOTAL)
TMAX
Figure 16. Typical Solder Heating Profile
8
Motorola TMOS Power MOSFET Transistor Device Data
MMDF3N03HD
PACKAGE DIMENSIONS
A B
M 8 5 X 45 _
J
1 4
4X
B
M_ G F
NOTES: 1. DIMENSIONS A AND B ARE DATUMS AND T IS A DATUM SURFACE. 2. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 3. DIMENSIONS ARE IN MILLIMETER. 4. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 5. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE. 6. DIMENSION D DOES NOT INCLUDE MOLD PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.35 0.49 0.40 1.25 1.27 BSC 0.18 0.25 0.10 0.25 0_ 7_ 5.80 6.20 0.25 0.50
P
0.25 (0.010)
M
T
8X
C
SEATING PLANE
D 0.25 (0.010)
M
K
T B
S
A
S
R
CASE 75105 SO8 ISSUE P
STYLE 11: PIN 1. 2. 3. 4. 5. 6. 7. 8.
SOURCE 1 GATE 1 SOURCE 2 GATE 2 DRAIN 2 DRAIN 2 DRAIN 1 DRAIN 1
Motorola TMOS Power MOSFET Transistor Device Data
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MMDF3N03HD
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Motorola TMOS Power MOSFET Transistor Device Data
*MMDF3N03HD/D*
MMDF3N03HD/D