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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4007UB gates Dual complementary pair and inverter Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Dual complementary pair and inverter DESCRIPTION HEF4007UB gates The HEF4007UB is a dual complementary pair and an inverter with access to each device. It has three n-channel and three p-channel enhancement mode MOS transistors. Fig.1 Schematic diagram. PINNING SP2, SP3 DP1, DP2 DN1, DN2 SN2, SN3 Fig.2 Pinning diagram. DN/P3 G1 to G3 HEF4007UBP(N): HEF4007UBD(F): HEF4007UBT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category GATES See Family Specifications for VIH/VIL unbuffered stages source connections to 2nd and 3rd p-channel transistors drain connections from the 1st and 2nd p-channel transistors drain connections from the 1st and 2nd n-channel transistors source connections to the 2nd and 3rd n-channel transistors common connection to the 3rd p-channel and n-channel transistor drains gate connections to n-channel and p-channel of the three transistor pairs January 1995 2 Philips Semiconductors Product specification Dual complementary pair and inverter AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays Gn DN ; DP HIGH to LOW 5 10 15 5 LOW to HIGH Output transition times HIGH to LOW 10 15 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL 40 20 15 40 20 15 60 30 20 60 30 20 80 40 30 75 40 30 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL TYP. MAX. HEF4007UB gates TYPICAL EXTRAPOLATION FORMULA 13 ns + (0,55 ns/pF) CL 9 ns + (0,23 ns/pF) CL 7 ns + (0,16 ns/pF) CL 13 ns + (0,55 ns/pF) CL 9 ns + (0,23 ns/pF) CL 7 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL VDD V Dynamic power dissipation per package (P) 5 10 15 TYPICAL FORMULA FOR P (µW) 4500 fi + (foCL) Ч VDD2 20 000 fi + (foCL) Ч 50 000 fi + (foCL) Ч VDD2 VDD2 where fi = input freq. (MHz) fo = output freq. (MHz) CL = load capacitance (pF) (foCL) = sum of outputs VDD = supply voltage (V) January 1995 3 Philips Semiconductors Product specification Dual complementary pair and inverter HEF4007UB gates Fig.3 Typical drain current ID and output voltage VO as functions of input voltage; VDD = 5 V; Tamb = 25 °C. Fig.4 Typical drain current ID and output voltage VO as functions of input voltage; VDD = 10 V; Tamb = 25 °C. Fig.5 Typical drain current ID and output voltage VO as functions of input voltage; VDD = 15 V; Tamb = 25 °C. January 1995 4 Philips Semiconductors Product specificatio