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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT40103 8-bit synchronous binary down counter Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jul 08 Philips Semiconductors Product specification 8-bit synchronous binary down counter FEATURES · Cascadable · Synchronous or asynchronous preset · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT40103 are high-speed Si-gate CMOS devices and are pin compatible with the "40103" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40103 consist each of an 8-bit synchronous down counter with a single output which is active when the internal count is zero. The "40103" contains a single 8-bit binary counter and has control inputs for enabling or disabling the clock (CP), for clearing the counter to its maximum count, and for presetting the counter either synchronously or asynchronously. All control inputs and the terminal count output (TC) are active-LOW logic. In normal operation, the counter is decremented by one count on each positive-going transition of the clock (CP). QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT40103 Counting is inhibited when the terminal enable input (TE) is HIGH. The terminal count output (TC) goes LOW when the count reaches zero if TE is LOW, and remains LOW for one full clock period. When the synchronous preset enable input (PE) is LOW, data at the jam input (P0 to P7) is clocked into the counter on the next positive-going clock transition regardless of the state of TE. When the asynchronous preset enable input (PL) is LOW, data at the jam input (P0 to P7) is asynchronously forced into the counter regardless of the state of PE, TE, or CP. The jam inputs (P0 to P7) represent a single 8-bit binary word. When the master reset input (MR) is LOW, the counter is asynchronously cleared to its maximum count (decimal 255) regardless of the state of any other input. The precedence relationship between control inputs is indicated in the function table. If all control inputs except TE are HIGH at the time of zero count, the counters will jump to the maximum count, giving a counting sequence of 256 clock pulses long. The "40103" may be cascaded using the TE input and the TC output, in either a synchronous or ripple mode. TYPICAL SYMBOL PARAMETER tPHL/ tPLH fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD Ч VCC2 Ч fi + (CL Ч VCC2 Ч fo) where: fi = input frequency in MHz fo = output frequency in MHz (CL Ч VCC2 Ч fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 V propagatio