SGS 40104 free download

File name 40104.pdf

HCC/HCF40104B HCC/HCF40194B 4-BIT BIDIRECTIONAL UNIVERSAL SHIFT REGISTER . . . . . . . . . . . MEDIUM-SPEED OPERATION : fCL = 9MHz (typ.) @ VDD = 10V FULLY STATIC OPERATION SYNCHRONOUS PARALLEL OR SERIAL OPERATION THREE-STATE OUTPUTS (HCC/HCF40104B) ASYNCHRONOUS MASTER RESET (HCC/HCF40194B) STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT AT 20V FOR HCC DEVICE 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N° 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIES CMOS DEVICES" EY (Plastic Package) F (Ceramic Package) C1 (Plastic Chip Carrier ) ORDER CODES : HCC401XXBF HCF401XXBEY HCF401XXBC1 DESCRIPTION The HCC40104B, HCC40194B, (extended temperature range) and the HCC40104B, HCF40194B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF 40104B is a universal shift register featuring parallel inputs, parallel outputs, SHIFT RIGHT and SHIFT LEFT serial inputs, and a high-impedance third output state allowing the device to be used in bus-organized systems. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift-right and shift-left are accomplished synchronously on the positive clock edge with serial data entered at the SHIFT RIGHT and SHIFT LEFT serial inputs, respectively. Clearing the register is accomplished by setting both mode controls low and clocking the register. When the output enable input is low, all outputs assume the high impedance state. The HCC/HCF40194B is a universal shift register featuring parallel inputs, parallel outputs SHIFT RIGHT and SHIFT LEFT serial inputs, and a direct overriding clear input. In the parallel-load mode (S0 and S1 are high), data is loaded into the associated flip-flop and June 1989 PIN CONNECTIONS 40104B 40194B 1/12 HCC/HCF40104B/40194B appears at the output after the positive transition of the CLOCK input. During loading, serial data flow is inhibited. Shift right and shift left are accomplished synchronously on the positive clock edge with data entered at the SHIFT RIGHT and SHIFT LEFT serial FUNCTIONAL DIAGRAMS 40104B 40194B inputs, respectively. Clocking of the register is inhibited when both mode control inputs are low. When low, the RESET input resets all stages and forces all outputs low. The HCC/HCF40194B is similar to industry types 340194 and MC40194. ABSOLUTE MAXIMUM RATINGS Symbol V DD * Vi II Pt o t Parameter Supply Voltage : H CC Types H C F Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for T o p = Full Package-temperature Range Operating Temperature : H CC Types H C F Types S