SGS 40108 free download

File name 40108.pdf

HCC40108B HCF40108B 4 x 4 MULTIPORT REGISTER . . . . . . . . . . . . . FOUR 4-BIT REGISTERS ONE INPUT AND TWO OUTPUT BUSES UNLIMITED EXPANSION IN BIT AND WORD DIRECTION DATA LINES HAVE LATCHED INPUTS 3-STATE OUTPUTS SEPARATE CONTROL OF EACH BUS, ALLOWING SIMULTANEOUS INDEPENDET READING AND ANY OF FOUR REGISTERS ON BUS A AND BUS B AND INDEPENDENT WRITING INTO ANY ANY OF THE FOUR REGISTERS 40108B IS PIN COMPATIBLE WITH INDUSTRY TYPE MC14580 STANDARDIZED, SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE 5V, 10V AND 15V PARAMETRIC RATINGS INPUT CURRENTOF 100 nA AT 18V AND 25oC FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD No 13a, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" no new data is netered. In either case, the contents of any word may be accessed via the read address lines independent of the state of the CLOCK input. EY (Plastic Package) F (Ceramic Package) M1 (Micro Package) C1 (Chip Carrier) ORDER CODES : HCC40108BF HCF40108BM1 HCF40108BEY HCF40108BC1 PIN CONNECTIONS DESCRIPTION The HCC40108B (extended temperature range) and HCF40108B (intermediate temperature range) are monolithic integrated circuits, available in 24 lead dual in line plastic or ceramic packageand plastic micropackage. The HCC/HCF40108B is a 4 X 4 multiport register containing four 4-bit register, write address decoder, two separate read address decoders, and two 3-state output buses. When the ENABLE input is low, the corresponding output bus is switched, independently of the clock, to a high impedance state. The high impedance third state provides the outputs with the capability of being connected to the bus lines in a bus organized system without the need for interface or pull-up components. When the WRITE ENABLE input is high, all data input lines are latched on the positive transition of the CLOCK and the data is entered into the word selected by the write address lines. When WRITE ENABLE is low, the CLOCK is inhibited and September 1988 1/14 HCC/HCF40108 FUNCTIONAL DIAGRAM LOGIC DIAGRAM 2/14 HCC/HCF40108 ABSOLUTE MAXIMUM RATING Symbol VDD * Vi II Ptot Parameter Supply Voltage: HCC Types HCF Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package Temperature Range Operating Temperature: HCC Types HCF Types Storage Temperature Value -0.5 to +20 -0.5 to +18 -0.5 to VDD + 0.5 ± 10 200 100 -55 to +125 -40 to +85 -65 to +150 Unit V V V mA mW mW o o o Top Tstg C C C Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ratingonly and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All volta