SGS 40161 free download

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HCC/HCF40160B-40161B HCC/HCF40162B-40163B SYNCHRONOUS PROGRAMMABLE 4-BIT COUNTERS 40160B CLEAR 40161B CLEAR 40162B CLEAR 40163B CLEAR - DECADE WITH ASYNCHRONOUS - BINARY WITH ASYNCHRONOUS - DECADE WITH SYNCHRONOUS - BINARY WITH SYNCHRONOUS EY (Plastic Package) F (Ceramic Package) . . . . . . . . . . INTERNAL LOOK-AHEAD FOR FAST COUNTING CARRY OUTPUT FOR CASCADING SYNCHRONOUSLY PROGRAMMABLE LOW-POWER TTL COMPATIBILITY STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC DEVICE 5V, 10V AND 15V PARAMETRIC RATINGS INPUT CURRENT OF 100nA AT 18V AND 25oC FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N. 13A, " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES " M1 (Micro Package) C1 (Chip Carrier) ORDER CODES : HCC40XXXBF HCF40XXXBEY HCF40XXXBC1 DESCRIPTION The HCC40160B, 40161B, 40162B, 40163B (extended temperature range) and HCF40160B, 40161B, 40162B, 40163B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in line plastic or ceramic package and plastic micropackage. HCC/HCF40160B, 40161B, 40162B and 40163B are 4-bit synchronous programmable counters. The CLEAR function of the HCC/HCF40162B and 40163B is synchronous and a low on the at the clear CLEAR input sets all four outputs low on the next positive CLOCK edge. The CLEAR function of the HCC/HCF40160B and 40161B is asynchronous and a low level at the CLEAR input sets all four outputs low regardless of the state of the CLOCK, LOAD or ENABLE inputs. A low level at the LOAD input disables the counter and causes the output to agree with the set-up data after the next CLOCK pulse regardless of the conditions of the ENABLE in- PIN CONNECTIONS September 1988 1/15 HCC/HCF40160B-40161B-40162-40163 cascading counter for n-bit synchronour application without additional gating. Instrumental in accomplishing this function are two count-enable input and a carry output (COUT). Counting is enable when both PE and TE inputs are high. The TE input is fed forward to enable COUT. This enable output ABSOLUTE MAXIMUM RATING Symbol VDD * Vi II Ptot Parameter Supply Voltage: HCC Types HCF Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for Top = Full Package Temperature Range Operating Temperature: HCC Types HCF Types Storage Temperature Value -0.5 to +20 -0.5 to +18 -0.5 to VDD + 0.5 ± 10 200 100 -55 to +125 -40 to +85 -65 to +150 Unit V V V mA mW mW o C o C o C produces a positive output pulse with a duration approximately equal to the positive portion of the Q1 output. This positive overflow carry pulse can be used to enable successive cascaded stages. Logic transitions at the PE or TE inputs may occur when the clock is either high or low. Top Tstg Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress ratingonly and