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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications 74HC/HCT40105 4-bit x 16-word FIFO register Product specification Supersedes data of December 1990 File under Integrated Circuits, IC06 1998 Jan 23 Philips Semiconductors Product specification 4-bit x 16-word FIFO register FEATURES · Independent asynchronous inputs and outputs · Expandable in either direction · Reset capability · Status indicators on inputs and outputs · 3-state outputs · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT40105 are high-speed Si-gate CMOS devices and are pin compatible with the "40105" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT40105 are first-in/first-out (FIFO) "elastic" storage registers that can store sixteen 4-bit words. The "40105" is capable of handling input and output data at QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf = 6 ns 74HC/HCT40105 different shifting rates. This feature makes it particularly useful as a buffer between asynchronous systems. Each word position in the register is clocked by a control flip-flop, which stores a marker bit. A "1" signifies that the position's data is filled and a "0" denotes a vacancy in that position. The control flip-flop detects the state of the preceding flip-flop and communicates its own status to the succeeding flip-flop. When a control flip-flop is in the "0" state and sees a "1" in the preceding flip-flop, it generates a clock pulse that transfers data from the preceding four data latches into its own four data latches and resets the preceding flip-flop to "0". The first and last control flip-flops have buffered outputs. Since all empty locations "bubble" automatically to the input end, and all valid data ripples through to the output end, the status of the first control flip-flop (data-in ready output - DIR) indicates if the FIFO is full, and the status of the last flip-flop (data-out ready output - DOR) indicates if the FIFO contains data. As the earliest data is removed from the bottom of the data stack (output end), all data entered later will automatically ripple toward the output. TYP. SYMBOL tPHL/ tPLH PARAMETER propagation delay MR to DIR, DOR SO to Qn tPHL propagation delay SI to DIR SO to DOR fmax CI CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD Ч VCC2 Ч fi + (CL Ч VCC2 Ч fo) where: fi = input frequency in MHz. fo = output frequency in MHz. (CL Ч VCC2 Ч fo) = sum of outputs CL = output load capacitance in pF VCC = supply voltage in V 2. For HC the condition is VI = GND to VCC For HCT the condition is VI = GND to VCC - 1.5 maximum clock frequency input capacitance power dissipation capacitance per package notes 1 and 2 16 17 33 3.5 134 18 18 31 3.5 145 ns ns MHz pF pF CONDITIONS HC CL = 15 pF; VCC = 5 V 16 37 15 35 ns ns HCT UNIT 1998 Jan 23 2 Philips Semiconductors Produ