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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4013B flip-flops Dual D-type flip-flop Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Dual D-type flip-flop DESCRIPTION The HEF4013B is a dual D-type flip-flop which features independent set direct (SD), clear direct (CD), clock inputs (CP) and outputs (O, O). Data is accepted when CP is LOW and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) are independent and override the D or CP inputs. The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FUNCTION TABLES INPUTS SD H L H CD L H H CP X X X D X X X HEF4013B flip-flops OUTPUTS O H L H O L H H INPUTS SD L L Notes CD L L CP D L H OUTPUTS On + 1 L H On + 1 H L 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition On + 1 = state after clock positive transition PINNING D CP SD CD O O data inputs clock input (L to H edge-triggered) asynchronous set-direct input (active HIGH) asynchronous clear-direct input (active HIGH) true output complement output Fig.1 Functional diagram. HEF4013BP(N): HEF4013BD(F): HEF4013BT(D): 14-lead DIL; plastic (SOT27-1) 14-lead DIL; ceramic (cerdip) (SOT73) 14-lead SO; plastic (SOT108-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category FLIP-FLOPS Fig.2 Pinning diagram. See Family Specifications January 1995 2 Philips Semiconductors Product specification Dual D-type flip-flop HEF4013B flip-flops January 1995 3 Fig.3 Logic diagram (one flip-flop). Philips Semiconductors Product specification Dual D-type flip-flop AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP O, O HIGH to LOW 5 10 15 5 LOW to HIGH SD O HIGH to LOW SD O LOW to HIGH CD O HIGH to LOW CD O LOW to HIGH 10 15 5 10 15 5 10 15 5 10 15 5 10 15 Output transition times HIGH to LOW 5 10 15 5 LOW to HIGH 10 15 tTLH tTHL tPLH tPHL tPLH tPHL tPLH tPHL 110 45 30 95 40 30 100 40 30 75 35 25 100 40 30 60 30 20 60 30 20 60 30 20 220 90 60 190 80 60 200 80 60 150 70 50 200 80 60 120 60 40 120 60 40 120 60 40 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns SYMBOL MIN. TYP. MAX. HEF4013B flip-flops TYPICAL EXTRAPOLATION FORMULA 83 ns + (0,55 ns/pF) CL 34 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 68 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 48 ns + (0,55 ns/pF) CL 24 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 73 ns + (0,55 ns/p