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HCF4018B PRESETTABLE DIVIDE-BY-N COUNTER s s s s s s s s MEDIUM SPEED OPERATION 10 MHz (Typ.) at VDD - VSS= 10V FULLY STATIC OPERATION STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B " STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE DIP SOP TUBE HCF4018BEY HCF4018BM1 T&R HCF4018M013TR DESCRIPTION The HCF4018B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. The HCF4018B consist of 5 Johnson counter stages, buffered Q outputs from each stage, and counter preset control gating. CLOCK, RESET, DATA, PRESET ENABLE, and 5 individual JAM inputs are provided. Divide by 10, 8, 6, 4 or 2 counter configuration can be implemented by feeding the Q5, Q4, Q3, Q2, Q1 signals, respectively, back to the data input. Divide-by-9, 7, 5, or 3 counter configurations can be implemented by the use of a HCF4011B gate PIN CONNECTION package to properly gate the feedback connection to the DATA input. Divide-by-functions greater than 10 can be achieved by use of multiple HCF4018B units. The counter is advanced one count at the positive clock signalstransition. Schmitt trigger action on the clock line permits unlimited clock rise and fall times. A high RESET signal clears the counter to an all-zero condition. A high PRESENT-ENABLE signal allows information on the JAM inputs to preset the counter. Anti-lock gating is provided to assure the proper counting sequence. September 2001 1/11 HCF4018B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 2, 3, 7, 9, 12 1 4, 5, 6, 11, 13 15 14 10 8 16 SYMBOL JAM1 to JAM5 DATA Q1 to Q5 RESET CLOCK PRESET ENABLE VSS VDD NAME AND FUNCTION Jam Inputs Data Input Buffered Outputs Reset Input Clock Input Preset Enable Input Negative Supply Voltage Positive Supply Voltage FUNCTIONAL DIAGRAM 2/11 HCF4018B LOGIC DIAGRAM TIMING CHART 3/11 HCF4018B ABSOLUTE MAXIMUM RATINGS Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 ± 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW °C °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V °C 4/11 HCF4018B DC SPECIFICATIONS Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO