File name 4021.pdfINTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4021B MSI 8-bit static shift register
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
8-bit static shift register
DESCRIPTION The HEF4021B is an 8-bit static shift register (parallel-to-serial converter) with a synchronous serial data input (DS), a clock input (CP), an asynchronous active HIGH parallel load input (PL), eight asynchronous parallel data inputs (P0 to P7) and buffered parallel outputs from the last three stages (05 to O7).
HEF4021B MSI
Each register stage is a D-type master-slave flip-flop with a set direct/clear direct input. Information on P0 to P7 is asynchronously loaded into the register while PL is HIGH, independent of CP and DS. When PL is LOW, data on DS is shifted into the first register position and all the data in the register is shifted one position to the right on the LOW to HIGH transition of CP. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
HEF4021BP(N): HEF4021BD(F): HEF4021BT(D):
16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America Fig.2 Pinning diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications PINNING PL P0 to P7 DS CP O5 to O7 parallel load input parallel data inputs serial data input clock input (LOW to HIGH edge-triggered) buffered parallel outputs from the last three stages
January 1995
2
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8-bit static shift register HEF4021B MSI
Philips Semiconductors
Product specification
8-bit static shift register
FUNCTION TABLES Serial operation INPUTS n 1 2 3 6 7 8 CP DS D1 D2 D3 X X X X PL L L L L L L L O5 X X X D1 D2 D3 OUTPUTS O6 X X X X D1 D2 no change O7 X X X X X D1 Notes n CP X
HEF4021B MSI
Parallel operation INPUTS DS X PL H O5 P5 OUTPUTS O6 P6 O7 P7
1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition = negative-going transition Dn = either HIGH or LOW n = number of clock pulse transitions
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP On HIGH to L |