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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4027B flip-flops Dual JK flip-flop Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Dual JK flip-flop DESCRIPTION The HEF4027B is a dual JK flip-flop which is edge-triggered and features independent set direct (SD), clear direct (CD), clock (CP) inputs and outputs (O,O). Data is accepted when CP is LOW, and transferred to the output on the positive-going edge of the clock. The active HIGH asynchronous clear-direct (CD) and set-direct (SD) are independent and override the J, K, and CP inputs. The outputs are buffered for best system performance. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. FUNCTION TABLES INPUTS SD H L H CD L H H CP X X X J X X X K X X X HEF4027B flip-flops OUTPUTS O H L H O L H H INPUTS SD L L L L Notes CD L L L L CP J L H L H K L L H H OUTPUTS On + 1 H L On On + 1 L H On no change 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state is immaterial = positive-going transition On + 1 = state after clock positive transition PINNING J,K CP SD CD O O synchronous inputs clock input (L to H edge-triggered) asynchronous set-direct input (active HIGH) asynchronous clear-direct input (active HIGH) true output complement output Fig.1 Functional diagram. HEF4027BP(N): HEF4027BD(F): HEF4027BT(D): 16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America FAMILY DATA, IDD LIMITS category FLIP-FLOPS See Family Specifications Fig.2 Pinning diagram. January 1995 2 Philips Semiconductors Product specification Dual JK flip-flop HEF4027B flip-flops Fig.3 Logic diagram (one flip-flop). AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays CP O, O HIGH to LOW 5 10 15 5 LOW to HIGH SD O LOW to HIGH CD O HIGH to LOW SD O HIGH to LOW 10 15 5 10 15 5 10 15 5 10 15 tPHL tPHL tPLH tPLH tPHL 105 40 30 85 35 30 70 30 25 120 45 35 140 55 40 210 ns 80 ns 60 ns 170 ns 70 ns 60 ns 140 ns 60 ns 50 ns 240 ns 90 ns 70 ns 280 ns 110 ns 80 ns 78 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 58 ns + (0,55 ns/pF) CL 27 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 43 ns + (0,55 ns/pF) CL 19 ns + (0,23 ns/pF) CL 17 ns + (0,16 ns/pF) CL 93 ns + (0,55 ns/pF) CL 33 ns + (0,23 ns/pF) CL 27 ns + (0,16 ns/pF) CL 113 ns + (0,55 ns/pF) CL 44 ns + (0,23 ns/pF) CL 32 ns + (0,16 ns/pF) CL SYMBOL MIN. TYP. MAX. TYPICAL EXTRAPOLATION FORMULA January 1995 3 Philips Semiconductors Product specification Dual JK flip-flop HEF4027B flip-flops VDD V SYMBOL MIN. TYP. 75 tPLH 35 25 60 tTHL 30 20 60 tTLH 50 tsu 30