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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4044B MSI Quadruple R/S latch with 3-state outputs Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs HEF4044B MSI The HEF4044B is a quadruple R/S latch with 3-state outputs with a common output enable input (EO). Each latch has an active LOW set input (S0 to S3), an active LOW reset input (R0 to R3) and an active HIGH 3-state output (O0 to O3). When EO is HIGH, the state of the latch output (On) can be determined from the function table below. When EO is LOW, the latch outputs are in the high impedance OFF-state. EO does not affect the state of the latch. Fig.2 Pinning diagram. The high impedance off-state feature allows common busing of the outputs. HEF4044BP(N): 16-lead DIL; plastic (SOT38-1) HEF4044BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4044BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America PINNING EO S0 to S3 R0 to R3 O0 to O3 common output enable input set inputs (active LOW) reset inputs (active LOW) 3-state buffered latch outputs FUNCTION TABLE INPUTS EO L H H H Notes 1. H = HIGH state (the more positive voltage) L = LOW state (the less positive voltage) X = state immaterial Z = high impedance OFF-state Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications Sn X L X H Rn X H L H OUTPUT On Z H L latched January 1995 2 Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs HEF4044B MSI Fig.4 Logic diagram (one latch). Fig.3 Logic diagram. January 1995 3 Philips Semiconductors Product specification Quadruple R/S latch with 3-state outputs AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays Rn On HIGH to LOW Sn On LOW to HIGH Output transition times HIGH to LOW LOW to HIGH 3-state propagation delays Output disable times EO On HIGH 5 10 15 5 LOW Output enable times EO On HIGH 5 10 15 5 LOW Minimum Sn pulse width; LOW Minimum Rn pulse width; LOW 10 15 5 10 15 5 10 15 tWRL tWSL 30 20 16 30 20 16 tPZL tPZH 50 25 20 50 25 20 15 10 8 15 10 8 100 ns 50 ns 40 ns 95 ns 45 ns 35 ns ns ns ns ns ns ns 10 15 tPLZ tPHZ 50 30 25 30 25 20 100 ns 60 ns 50 ns 60 ns 45 ns 40 ns 5 10 15 5 10 15 5 10 15 5 10 15 tTLH tTHL tPLH tPHL 90 40 30 90 40 30 60 30 20 60 30 20 185 ns 80 ns 60 ns 180 ns 80 ns 60 ns 120 ns 60 ns 40 ns 120 ns 60 ns 40 ns SYMBOL MIN. TYP. MAX. HEF4044B MSI TYPICAL EXTRAPOLATION FORMULA 63 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 63 ns + (0,55 ns/pF) CL 29 ns + (0,23 ns/pF) CL 22 ns + (0,16 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns + (0,28 ns/pF) CL 10 ns + (1,0 ns/pF) CL 9 ns + (0,42 ns/pF) CL 6 ns