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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications · The IC06 74HC/HCT/HCU/HCMOS Logic Package Information · The IC06 74HC/HCT/HCU/HCMOS Logic Package Outlines 74HC/HCT4059 Programmable divide-by-n counter Product specification Supersedes data of September 1993 File under Integrated Circuits, IC06 1998 Jul 08 Philips Semiconductors Product specification Programmable divide-by-n counter FEATURES · Synchronous programmable divide-by-n counter · Presettable down counter · Fully static operation · Mode select control of initial decade counting function (divide-by-10, 8, 5, 4 and 2) · Master preset initialization · Latchable output · Easily cascadable with other counters · Four operating modes: timer divider-by-n divide-by-10 000 master preset · Output capability: standard · ICC category: MSI GENERAL DESCRIPTION The 74HC/HCT4059 are high-speed Si-gate CMOS devices and are pin compatible with the "4059" of the "4000B" series. They are specified in compliance with JEDEC standard no. 7A. The 74HC/HCT4059 are divide-by-n counters which can be programmed to divide an input frequency by any number (n) from 3 to 15 999. There are four operating modes, timer, divide-by-n, divide-by-10 000 and master preset, which are defined by the mode select inputs (Ka to Kc) and the latch enable input (LE) as shown in the Function table. The complete counter consists of a first counting stage, an intermediate counting stage and a fifth counting stage. The first counter stage consists of four independent flip-flops. Depending on the divide-by-mode, at least one flip-flop is placed at the input of the intermediate stage (the remaining flip-flops are placed at the fifth stage with a place value of thousands). The intermediate stage consists of three cascaded decade counters, each containing four flip-flops. All flip-flops can be preset to a desired state by means of the JAM inputs (J1 to J16), during which the clock input (CP) will cause all stages to count from n to zero. The zero-detect circuit will then cause all stages to return to the JAM count, during which an output pulse is generated. In the timer mode, after an output pulse is generated, the output pulse remains HIGH until the latch input (LE) goes LOW. The counter will advance, even if LE is HIGH and the output is latched in the HIGH state. 74HC/HCT4059 In the divide-by-n mode, a clock cycle wide pulse is generated with a frequency rate equal to the input frequency divided by n. The function of the mode select and JAM inputs are illustrated in the following examples. In the divide-by-2 mode, only one flip-flop is needed in the first counting section. Therefore the last (5th) counting section has three flip-flops that can be preset to a maximum count of seven with a place value of thousands. This counting mode is selected when Ka to Kc are set HIGH. In this case input J1 is used to preset the first counting section and J2 to