File name 4060.pdfINTEGRATED CIRCUITS
DATA SHEET
For a complete data sheet, please also download:
· The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC
HEF4060B MSI 14-stage ripple-carry binary counter/divider and oscillator
Product specification File under Integrated Circuits, IC04 January 1995
Philips Semiconductors
Product specification
14-stage ripple-carry binary counter/divider and oscillator
DESCRIPTION The HEF4060B is a 14-stage ripple-carry binary counter/divider and oscillator with three oscillator terminals (RS, RTC and CTC), ten buffered outputs (O3 to O9 and O11 to O13) and an overriding asynchronous master reset input (MR). The oscillator configuration allows design of either RC or crystal oscillator circuits. The oscillator may
HEF4060B MSI
be replaced by an external clock signal at input RS. The counter advances on the negative-going transition of RS. A HIGH level on MR resets the counter (O3 to O9 and O11 to O13 = LOW), independent of other input conditions. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times.
Fig.1 Functional diagram.
PINNING MR RS RTC CTC O3 to O9 O11 to O13 master reset clock input/oscillator pin oscillator pin external capacitor connection counter outputs
HEF4060BP(N): HEF4060BD(F): Fig.2 Pinning diagram. HEF4060BT(D):
16-lead DIL; plastic (SOT38-1) 16-lead DIL; ceramic (cerdip) (SOT74) 16-lead SO; plastic (SOT109-1)
( ): Package Designator North America FAMILY DATA, IDD LIMITS category MSI See Family Specifications
January 1995
2
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14-stage ripple-carry binary counter/divider and oscillator HEF4060B MSI
Philips Semiconductors
Product specification
14-stage ripple-carry binary counter/divider and oscillator
AC CHARACTERISTICS VSS = 0 V; Tamb = 25 °C; CL = 50 pF; input transition times 20 ns VDD V Propagation delays RS O3 HIGH to LOW 5 10 15 5 LOW to HIGH On On + 1 HIGH to LOW 10 15 5 10 15 5 LOW to HIGH MR On HIGH to LOW Output transition times HIGH to LOW LOW to HIGH Minimum clock pulse width input RS HIGH Minimum MR pulse width; HIGH Recovery time for MR Maximum clock pulse frequency input RS 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 5 10 15 fmax tRMR tWMRH tWRSH 120 50 30 50 30 20 160 80 60 4 10 15 tTLH tTHL tPHL tPLH tPHL tPLH tPHL 210 80 50 210 80 50 25 10 6 25 10 6 100 40 30 60 30 20 60 30 20 60 25 15 25 15 10 80 40 30 8 20 30 420 160 |