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Application Note 106 Software Customization for the 6x86TM Family Applicable to the Entire Line of 6x86TM Cyrix® Processors. Rev 1.5. APPLICATION NOTE 106 Software Customization for the 6x86 Family 1. Introduction This document provides guidance in writing effective software for the Cyrix 6x86TM and 6x86MXTM processors. Differences between 6x86 and 6x86MX CPUs are listed in Appendix A. The Cyrix Software Developer web site (www.cyrix.com) provides current information and code examples on topics such as CPU Detection and Cache Line Locking. 1.1. No Instruction-Pair Optimization Needed It is important to point out, that the Cyrix 6x86 and 6x86MX require no instruction-pair optimization as does the Pentium® CPU. The reason is that the execution pipelines in the 6x86/6x86MX are more balanced than those in the Pentium. Both legacy 16-bit code, and Pentium optimized 32-bit code pass through the Cyrix execution pipelines with the same efficiency. 2 Application Note 106 -Software Customization for the 6x86 Family, Rev 1.5 Remove Address Generation Interlocks 2. 6x86 Family Coding Suggestions The suggestions in this section will help both the programmer to produce higher performance software when using the 6x86 and the 6x86MX processors. 2.1. Remove Address Generation Interlocks Separate Address Generation Interlocks (AGIs) by 2 cycles (2 to 4 instructions). For example, avoid: add cx,bx add dx,[cx] In this example cx in the second instruction cannot be used until the cx in the first instruction is finished updating. This coding will produce a two clock bubble which results in a four instruction penalty. Another common example to avoid: mov eax,[eax] mov eax,[eax] mov eax,[eax] cmp eax,whatever 2.2. Don't Move Variables Into Registers For Speed It has been a common practice to place frequently used variables into the CPU general purpose registers (EAX, EBX, ECX, EDX). This was done because register access was the far quicker than cache access. This practice is not needed for 6x86 architecture CPUs. The 6x86 L1 cache access time is the same as register access time. This also reduces "register pressure" limitations in the compiler. Application Note 106 -Software Customization for the 6x86 Family, Rev 1.5 3 Avoiding RISC-like Instruction Coding, Complex is Better 2.3. Avoiding RISC-like Instruction Coding, Complex is Better For the CPUs that have pairing constraints, optimization of code consists of partly of turning CISC instructions into RISC-like instruction equivalents. The RISC equivalents increase code size that end up taking more space in the cache. The 6x86 and 6x86MX are designed to accelerate complex x86 instructions and do not have pair optimization constraints. For this reason, it is recommended not to break complex instructions into RISC equivalents for 6x86 family of CPUs. The instruction below takes only one clock cycle to execute. add [mem], eax If this instruction is broken into three RISC-like instructions three clock cy