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HCF4089B BINARY RATE MULTIPLIER s s s s s s s s CASCADABLE IN MULTIPLES OF 4-BITS SET TO "15" INPUT AND "15" DETECT OUTPUT QUIESCENT CURRENT SPECIFIED UP TO 20V STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE DIP SOP TUBE HCF4089BEY HCF4089BM1 T&R HCF4089M013TR DESCRIPTION HCF4089B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4089B is a low power 4-bit digital rate multiplier that provides an output pulse rate that is the clock input pulse rate multiplied by 1/16 times the binary input. For example, when the binary input number is 13, ther will be 13 output pulses for every 16 input pulses. HCF4089B has an internal synchronous 4-bit counter, which, together with one of the four binary inputs bits, produces pulse trains as shown in the timing diagram. If more than one binary input bit is high, the resulting pulse train is a combination of the above separate pulse trains. This device may be used to perform arithmetic operations (add, subtract, divide, raise to a power), solve algebrical and differential equations, generate natural logarithms and trigonometric functions, A/D and D/A conversions, and frequency division. PIN CONNECTION September 2002 1/11 HCF4089B IINPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 14, 15, 2, 3 5 6 4 1 7 13 12 11 10 9 8 16 SYMBOL A, B, C, D OUT OUT SET TO "15" "15" OUT INHIBIT OUT (CARRY) CLEAR CASCADE INHIBIT IN (CARRY) STROBE CLOCK VSS VDD NAME AND FUNCTION Binary Rate Select Inputs Rate Output Rate Output Set Input Output Inhibit Out (Carry) Clear Input Cascade Inhibit Input (Carry) Strobe Clock Input Negative Supply Voltage Positive Supply Voltage FUNCTIONAL DIAGRAM 2/11 HCF4089B TRUTH TABLE INPUTS Number of Pulses or Input Logic Level D L L L L L L L L H H H H H H H H X X X H L X C L L L L H H H H L L L L H H H H X X X X X X B L L H H L L H H L L H H L L H H X X X X X X A L H L H L H L H L H L H L H L H X X X X X X CLOCK 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 16 INH IN L L L L L L L L L L L L L L L L H L L L L L STR. L L L L L L L L L L L L L L L L L H L L L L CAS. L L L L L L L L L L L L L L L L L L H L L L CLEAR L L L L L L L L L L L L L L L L L L L H H L SET L L L L L L L L L L L L L L L L L L L L L H OUTPUTS Number of Pulses or Output Logic Level OUT L 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 · L H 16 L L OUT H 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 · H * 16 H H INH OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 H 1 1 H H L "15" OUT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 · 1 1 L L H X : Don't Care · : Depends on internal state of counter *: Output same as the first 16 lines of this truth table (depending on values of A, B, C, D) LOGIC DIAGRAM 3/11 HCF4089