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HCF4096B GATED J-K MASTER SLAVE FLIP-FLOP s s s s s s s 16MHz TOGGLE RATE (Typ.) at VDD - VSS = 10V GATED INPUTS QUIESCENT CURRENT SPECIFIED UP TO 20V 5V, 10V AND 15V PARAMETRIC RATINGS INPUT LEAKAGE CURRENT II = 100nA (MAX) AT VDD = 18V TA = 25°C 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC JESD13B "STANDARD SPECIFICATIONS FOR DESCRIPTION OF B SERIES CMOS DEVICES" DIP SOP ORDER CODES PACKAGE DIP SOP TUBE HCF4096BEY HCF4096BM1 T&R HCF4096M013TR DESCRIPTION HCF4096B is a monolithic integrated circuit fabricated in Metal Oxide Semiconductor technology available in DIP and SOP packages. HCF4096B is a J-K Master-Slave Flip-Flop featuring separate AND gating of multiple J and K inputs. The gated J-K input control transfers information into the master section during clocked operation. Information on the J-K inputs is transferred to the Q and Q outputs on the positive edge of the clock pulse. SET and RESET inputs (active high) are provided for asynchronous operation. PIN CONNECTION September 2002 1/10 HCF4096B INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION PIN No 3, 4, 5 11, 10, 9 8 6 13 2 12 1 7 14 SYMBOL J1, J2, J3 K1, K2, K3 Q Q SET (S) RESET (R) CLOCK NC VSS VDD NAME AND FUNCTION J Inputs K Inputs Q Output Q Output Set Inputs(Active High) Reset Inputs(Active High) Clock Inputs Not Connected Negative Supply Voltage Positive Supply Voltage TRUTH TABLE : SYNCHRONOUS OPERATION (S=0 R=0) INPUTS BEFORE POSITIVE CLOCK TRANSITION J* L L H H (*) : J=J1 · J2 · J3, K=K1 · K2 · K3 OUTPUTS AFTER POSITIVE CLOCK TRANSITION Q NO CHANGE L H TOGGLES H L Q K* L H L H TRUTH TABLE : ASYNCHRONOUS OPERATION (J and K DON'T CARE) INPUTS BEFORE POSITIVE CLOCK TRANSITION S L L H H (*) : L = Vss, H = Vdd OUTPUTS AFTER POSITIVE CLOCK TRANSITION Q NO CHANGE L H L H L L Q R L H L H 2/10 HCF4096B FUNCTIONAL DIAGRAM LOGIC DIAGRAM 3/10 HCF4096B ABSOLUTE MAXIMUM RATINGS Symbol VDD VI II PD Top Tstg Supply Voltage DC Input Voltage DC Input Current Power Dissipation per Package Power Dissipation per Output Transistor Operating Temperature Storage Temperature Parameter Value -0.5 to +22 -0.5 to VDD + 0.5 ± 10 200 100 -55 to +125 -65 to +150 Unit V V mA mW mW °C °C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol VDD VI Top Supply Voltage Input Voltage Operating Temperature Parameter Value 3 to 20 0 to VDD -55 to 125 Unit V V °C DC SPECIFICATIONS Test Condition Symbol Parameter VI (V) 0/5 0/10 0/15 0/20 0/5 0/10 0/15 5/0 10/0 15/0 0.5/4.5 1/9 1.5/13.5 4.5/0.5 9/1 13.5/1.5 2.5 4.6 9.5 13.5 0.4 0.5 1.5 VO (V) |IO| VDD (µA) (V) 5 10 15 20 5 10 15 5 10 15 5 10 15 5 10 15 5 5 10 15 5 10 15 TA = 25°C Min. Typ. 0.02 0.02 0.02 0.04 4.95 9.95 14.95 0.05 0.05 0.05 3.5 7 11 1.5 3 4 -1.36 -0.44 -1.1 -3.0 0.44 1.1 3.0 -3.2 -1 -2.6 -6.8 1 2.6 6.8 -1.15 -0.36 -0.9 -2.4 0.36