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File name:4099.pdf
Size:303 kB
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Mfg:SGS
Model:4099 🔎
Original:CMOS 4xxx 🔎
Descr:8-BIT ADDRESSABLE LATCH
Group:Electronics > Components > Integrated circuits
Uploaded:20-05-2005
User:dupator
Multipart:No multipart

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File name 4099.pdf

HCC/HCF4099B 8-BIT ADDRESSABLE LATCH . . . . . . . . . SERIAL DATA INPUT - ACTIVE PARALLEL OUTPUT STORAGE REGISTER CAPABILITY - MASTER CLEAR CAN FUNCTION AS DEMULTIPLEXER STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE 5V, 10V, AND 15V PARAMETRIC RATINGS INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N°. 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIES CMOS DEVICES" EY Plastic Package F Ceramic Frit Seal Package M1 Micro Package C1 Plastic Chip Carrier ORDER CODES : HCC4099BF HCF4099BM1 HCF4099BEY HCF4099BC1 PIN CONNECTIONS DESCRIPTION The HCC4099B (extended temperature range) and HCF4099B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4099B 8-bit addressable latch is a serial-input, parallel-output storage register that can perform a variety of functions. Data are inputted to a particular bit in the latch when that bit is addressed (by means of inputs A0, A1, A2) and when WRITE DISABLE is at a low level. When WRITE DISABLE is high, data entry is inhibited ; however, all 8 outputs can be continuously read independent of WRITE DISABLE and address inputs. A master RESET input is available, which resets all bits to a logic "0" level when RESET and WRITE DISABLE are at a high level. When RESET is at a high level, and WRITE DISABLE is at a low level, the latch acts as a 1-of-8 demultiplexer ; the bit that is addressed has an active output which follows the data input, while all unaddressed bits are held to a logic "0" level. September 1988 1/14 HCC/HCF4099B FUNCTIONAL DIAGRAM ABSOLUTE MAXIMUM RATINGS Symbol V DD* Vi II Pt ot Parameter Supply Voltage : HC C Types H C F Types Input Voltage DC Input Current (any one input) Total Power Dissipation (per package) Dissipation per Output Transistor for T o p = Full Package-temperature Range Operating Temperature : HCC Types H CF Types Storage Temperature Value ­ 0.5 to + 20 ­ 0.5 to + 18 ­ 0.5 to V DD + 0.5 ± 10 200 100 ­ 55 to + 125 ­ 40 to + 85 ­ 65 to + 150 Unit V V V mA mW mW °C °C °C Top Tstg Stresses above listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for external periods may affect device reliability. * All voltage values are referred to VSS pin voltage. RECOMMENDED OPERATING CONDITIONS Symbol V DD VI Top Parameter Supply Voltage : HCC Types H CF Types Input Voltage Operating Temperature : HCC Types HC F Types Value 3 to 18 3 to 15 0 to V DD ­ 55 to + 125 ­ 40 to + 85 Unit V V V °C °C 2/14 HCC/HCF4099B LOGIC DIAGRAM 1 of 8 latches Definition of WRITE

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