Philips 4521 free download

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4521B MSI 24-stage frequency divider and oscillator Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification 24-stage frequency divider and oscillator DESCRIPTION The HEF4521B consists of a chain of 24 toggle flip-flops with an overriding asynchronous master reset input (MR), and an input circuit that allows three modes of operation. The single inverting stage (I2/O2) will function as a crystal oscillator, or in combination with I1 as an RC oscillator, or as an input buffer for an external oscillator. Low-power HEF4521B MSI operation as a crystal oscillator is enabled by connecting external resistors to pins 3 (VSS') and 5 (VDD'). Each flip-flop divides the frequency of the previous flip-flop by two, consequently the HEF4521B will count up to 224 = 16777216. The counting advances on the HIGH to LOW transition of the clock (I2). The outputs of the last seven stages are available for additional flexibility. Fig.1 Functional diagram. FAMILY DATA, IDD LIMITS category MSI See Family Specifications January 1995 2 Philips Semiconductors Product specification 24-stage frequency divider and oscillator COUNT CAPACITY HEF4521B MSI OUTPUT O18 O19 O20 O21 Fig.2 Pinning diagram. O22 O23 O24 HEF4521BP(N): 16-lead DIL; plastic (SOT38-1) HEF4521BD(F): 16-lead DIL; ceramic (cerdip) (SOT74) HEF4521BT(D): 16-lead SO; plastic (SOT109-1) ( ): Package Designator North America 218 219 COUNT CAPACITY = 262 144 = 524 288 220 = 1 048 576 221 = 2 097 152 222 = 4 194 304 223 = 8 388 608 224 = 16 777 216 FUNCTIONAL TEST SEQUENCE INPUTS MR H I2 L O2 L CONTROL TERMINALS VSS' VDD VDD' VSS OUTPUTS REMARKS O18 to O24 L counter is in three 8-stage sections in parallel mode; I2 and O2 are interconnected (O2 is now input); counter is reset by MR 255 pulses are clocked into I2, O2 (the counter advances on the LOW to HIGH transition) VSS' is connected to VSS the input I2 is made HIGH VDD' is connected to VDD; O2 is now made floating and becomes an output; the device is now in the 224 mode counter ripples from an all HIGH state to an all LOW state L VDD VSS H L L L L H H L L L VSS VSS VSS VSS VSS VDD H H H L VSS VDD L A test function has been included for the reduction of the test time required to exercise all 24 counter stages. This test function divides the counter into three 8-stage sections by connecting VSS' to VDD and VDD' to VSS. Via I2 (connected to O2) 255 counts are loaded into each of the 8-stage sections in parallel. All flip-flops are now at a HIGH state. The counter is now returned to the normal 24-stage in series configuration by connecting VSS' to VSS and VDD' to VDD. One more pulse is entered into input I2, which will cause the counter to ripple from an all HIGH st