Philips TDA8044A free download

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INTEGRATED CIRCUITS DATA SHEET TDA8044; TDA8044A Satellite demodulator and decoder Preliminary specification Supersedes data of 1998 Apr 07 File under Integrated Circuits, IC02 1998 Nov 17 Philips Semiconductors Preliminary specification Satellite demodulator and decoder FEATURES · General features: ­ One chip DVB compliant QPSK/BPSK demodulator and concatenated Viterbi/Reed-Solomon decoder with de-interleaver and de-randomizer (ETS 300 421) ­ 3.3 V supply voltage (input pads are 5 V tolerant) ­ Stand-by mode for low power dissipation ­ Internal clock PLL to allow low frequency crystal application and selectable clock frequencies ­ Power-on reset module ­ Package: QFP100 ­ Boundary Scan Test. · QPSK/BPSK demodulator: ­ Interpolator and anti-alias filter to handle a large range of symbol rates without additional external filtering ­ On-chip AGC of the analog input I&Q baseband signals or tuner AGC control. ­ Two on-chip matched A-D converters (7 bits) ­ Half Nyquist (square-root raised-cosine) filter with selectable roll-off factor ­ Large range of symbol frequencies: 0.5 to 45 Msymbols/s for TDA8044 and 0.5 to 30 Msymbols/s for TDA8044A, including SCPC (Single Carrier Per Channel) function ­ Can be used at low channel Signal to Noise Ratio (SNR) ­ Internal carrier recovery, clock recovery and AGC loops with programmable loop filters ­ Two loop carrier recovery enabling phase tracking of the incoming symbols ­ Software carrier sweep for low symbol rate applications ­ SNR estimation ­ External indication of demodulator lock. · Viterbi decoder: ­ Rate 1/2 convolutional code based ­ Constraint length K = 7 with G1 = 171oct and G2 = 133oct.Supported puncturing code rates: 1/2, 2/3, 3/4, 4/5, 5/6, 6/7, 7/8, 8/9 ­ 4 bits input for `soft decision' for both I and Q APPLICATIONS TDA8044; TDA8044A ­ Truncation length: 144 ­ Automatic synchronisation ­ Channel BER estimation ­ External indication of Viterbi sync lock ­ Differential decoding optional. · Reed-Solomon decoder: ­ (204, 188, T = 8) Reed-Solomon code ­ Automatic (I2C configurable) synchronisation of bytes, transport packets and frames ­ Internal convolutional de-interleaving (I = 12; using internal memory) ­ De-randomizer based on PRBS ­ External indication of RS decoder sync lock ­ External indication of uncorrectable error; (Transport Error Indicator is set) ­ External indication of corrected byte ­ Indication of the number of lost blocks ­ Indication of the number of corrected blocks. · Interface: ­ I2C-bus interface to initialize and monitor the demodulator and FEC decoder. When no I2C usage, default mode is defined ­ Programmable interrupt facility ­ Six bits I/O expander for flexible access to and from the I2C-bus ­ Switchable I2C loop-through to suppress I2C crosstalk in the tuner ­ DiSEqC level 1.X support for dish control applications ­ 3-state mode for transport stream outputs. · Digital satellite TV: demodulation and forward error correction (FEC). 1998 Nov 17 2 Philips Semic