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File name: | SY31-0458-3_Section_04_Interrupts_and_Cycle_Steal.pdf [preview SY31-0458-3 Section 04 Interrupts and Cycle Steal] |
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Model: | SY31-0458-3 Section 04 Interrupts and Cycle Steal 🔎 |
Original: | SY31-0458-3 Section 04 Interrupts and Cycle Steal 🔎 |
Descr: | IBM system34 fe SY31-0458-3_System_34_5340_System_Unit_Theory_Diagrams_Manual_Jul79 SY31-0458-3_Section_04_Interrupts_and_Cycle_Steal.pdf |
Group: | Electronics > Consumer electronics > Audio > Professional |
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File name SY31-0458-3_Section_04_Interrupts_and_Cycle_Steal.pdf Contents INTERRUPTS AND CYCLE STEAL REQUESTS 4-1 INTERRUPTS . . . . . . . 4-1 Local Storage Register Stack 4- 2 Interrupt Levels . . . . . . 4-3 Interrupt Level 0 4-3 Interrupt Level 1-Disk and Diskette 4-3 Interrupt Level 2-Communications and Fixed Interval Timer 4-3 Interrupt Level 3 4-3 Interrupt Level 4 4-3 Interrupt Level 5 4-3 Main Program Level Interrupt. 4-3 Interrupti Cycle Steal Priority Encode and LSR Selection 4-4 MSP Set Interrupt Level 5 . 4-5 CONTROL PROCESSOR AND MAIN STORAGE PROCESSOR COMMUNICATION 4-6 CONTROL PROCESSOR AND CHANNEL COMMUNICATION. . . . . . . . . . 4-7 Contents for Interrupts and Cycle Steal Requests Interrupts and Cycle Steal Requests INTERRUPTS The control processor executes instructions one Priority Interrupt Level or Function If the control processor is not working with' All interrupt levels use the same processor at a time; one instruction is followed by the Cycle Steal interrupts, it is executing instructions on the condition register; therefore, the processor next sequential instruction. This sequence of Request main program level. condition register must be saved when entering instructions can be changed by executing a Interrupt 0 Machine check routines an interrupt level and then restored when branch or jump instruction. The sequence can Each interrupt level and the main program level leaving the interrupt level. This process ensures also be changed by passing control from (1) 2 Burst cycle steal Disk data movement has a set of re,gisters in the local storage that the contents of the processor condition one interrupt level to another interrupt level of register stack. Interrupt level 0 and the main register are correctly associated with the higher priority, or (2) to the main program level. 3(note) Base cycle steal 5251 Display Station program level use the same set of work interrupt level in process. (If the interrupt level registers. program does not change the processor The contr |
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