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® L6269 12V DISK DRIVE SPINDLE & VCM, POWER & CONTROL "COMBO" PRODUCT PREVIEW GENERAL 12V (+/- 10%) OPERATION. REGISTER BASED ARCHITECTURE MINIMUM EXTERNAL COMPONENTS BICMOS + VERTICAL DMOS (1.5mm) VCM DRIVER 1.5A DRIVE CAPABILITY 0.9W TOTAL BRIDGE IMPEDANCE AT 25°C LINEAR MODE PHASE SHIFT MODULATION (PWM MODE) INSTANTANEOUS, (GLICH FREE) SWITCH BETWEEN THE 2 MODES CLASS AB OUTPUT DRIVERS ZERO CROSSOVER DISTORSION 14 BIT DAC DEFINE OUTPUT CURRENT SELECTABLE TRANSCONDUCTANCE 4 PROGRAMMABLE PARKING VOLTAGE DYNAMIC BRAKE SPINDLE DRIVER 2.0A DRIVE CAPABILITY 0.8W TOTAL BRIDGE IMPEDANCE AT 25°C BEMF, INTERNAL OR EXTERNAL, PROCESSING SENSOR-LESS MOTOR COMMUTATION PROGRAMMABLE COMMUTATION PHASE DELAY LINEAR MODE AND CONSTANT TOFF PWM OPERATION MODE INTERNAL FREQUENCY LOCKED LOOP SPEED CONTROL (FLL) BEMF RECTIFICATION DURING RETRACT BUILT-IN ALIGNAMENT&GO START-UP INDUCTIVE SENSING START UP OPTION RESYNCHRONIZATION DYNAMIC & REVERSE BRAKE CONTROLLABLE OUTPUT SLEW RATE OTHER FUNCTIONS 12V AND 5V MONITORING WITH EXTERNAL SET TRIP POINTS AND HYSTERESIS POWER UP/DOWN SEQUENCING BICMOS TECHNOLOGY TQFP44 (10x10mm) ORDERING NUMBER: L6269 LOW VOLTAGE SENSE 3.3V INPUT LOGIC COMPATIBILITY THERMAL SHUTDOWN AND PRETHERMAL WARNING DESCRIPTION The L6269 integrates into a single chip both spindle and VCM controllers as well as power stages. The device is designed for 12V disk drive application requiring up to 2.0A of spindle and 1.5A of VCM peak currents. A serial port with up to 25 MHz capability provides easy interface to the microprocessor. A register controlled Frequency Locked Loop (FLL) allows flexibility in setting the spindle speed. Integrated BEMF processing, digital masking, digital delay, and sequencing minimize the number of external components required. Power On Reset (POR) circuitry is included. Upon detection of a low voltage condition, POR is asserted, the internal registers are reset, and spindle power circuitry is tri-stated. The BEMF is rectified providing power for actuator retraction followed by dynamic spindle braking. The device is built in BICMOS technology allowing dense digital/analog circuitry to be combined with a high power DMOS output stage. April 1999 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/17 L6269 BLOCK DIAGRAM FLL_FILTER SPN_COMP PWM/SLEW BRK_CAP SYS_CLK FLL_RES INDEX FCOM CS CHARGE PUMP FREQUENCY LOCK LOOP SPINDLE SEQUENCER VCC CP A OUT_A CTAP START-UP SW1 ISO DRIVER RE_SYNC BEMF PROCESSING ZERO CROSS DETECTION SPINDLE CURRENT CONTROL PWM/LIN B OUT_B RSENSE C OUT_C ISENSE SDATA SERIAL INTERFACE DYNAMIC/ REVERSE BRAKE SCLK REGISTERS VCM CURRENT CONTROL PSM/LIN VCM CALIBRATION PARKING BEMF RECTIFICATION A+ VCM_A+ VCC SDEN A- VCM_AVCM_GND TR_12V TR_5V SUPPLY FAULT MONITORS THERMAL SUPPLY 14 BIT VCM DAC REFERENCE VOLTAGE GENERATOR + - A=4 + SENSE_INSENSE_IN+ DGND ERROR_IN ERROR_OUT V12/2 POR_DELAY VCM_CAL VDD PORB