Philips TDA4662 free download

File name Tda4662.pdf

INTEGRATED CIRCUITS DATA SHEET TDA4662 Baseband delay line Product specification Supersedes data of 1995 Oct 30 File under Integrated Circuits, IC02 1996 Nov 14 Philips Semiconductors Product specification Baseband delay line FEATURES · Two comb filters, using the switched-capacitor technique, for one line delay time (64 µs) · For PAL and NTSC · Adjustment-free application · Handles negative or positive colour-difference input signals · Clamping of AC-coupled input signals [±(R-Y) and ±(B-Y)] · VCO without external components · 3 MHz internal clock signal derived from a 6 MHz CCO, line-locked by the sandcastle pulse (64 µs line) · Sample-and-hold circuits and low-pass filters to suppress the 3 MHz clock signal · Addition of delayed and non-delayed output signals · Output buffer amplifiers · Comb filtering functions for NTSC colour-difference signals to suppress cross-colour. QUICK REFERENCE DATA SYMBOL VP1 VP2 IP(tot) Vi(p-p) Gv PARAMETER analog supply voltage (pin 9) digital supply voltage (pin 1) total supply current MIN. 4.5 4.5 - 5 5 5.5 525 665 5.8 5.8 TYP. 6 6 GENERAL DESCRIPTION TDA4662 The TDA4662 is an integrated baseband delay line circuit with one line delay. It is suitable for PAL and NTSC decoders with colour-difference signal outputs ±(R-Y) and ±(B-Y). MAX. V V UNIT 7.0 - - 6.3 6.3 mA mV mV dB dB ±(R-Y) input signal PAL/NTSC (peak-to-peak value; pin 16) - ±(B-Y) input signal PAL/NTSC (peak-to-peak value; pin 14) - voltage gain VO/VI of colour-difference output signals V11/V16 for PAL and NTSC V12/V14 for PAL and NTSC 5.3 5.3 ORDERING INFORMATION TYPE NUMBER TDA4662 TDA4662T PACKAGE NAME DIP16 SO16 DESCRIPTION plastic dual in-line package; 16 leads (300 mil) plastic small outline package; 16 leads; body width 3.9 mm VERSION SOT38-4 SOT109-1 1996 Nov 14 2 1996 Nov 14 BLOCK DIAGRAM Philips Semiconductors Baseband delay line handbook, full pagewidth ±(R-Y) 11 LP addition output stages buffers ±(R-Y) LINE MEMORY pre-amplifiers SAMPLEAND-HOLD 16 SIGNAL CLAMPING colour-difference input signals colour-difference output signals ±(B-Y) LINE MEMORY SAMPLEAND-HOLD LP 14 SIGNAL CLAMPING 12 3 3 MHz shifting clock DIVIDEBY-192 ±(B-Y) VP1 FREQUENCY PHASE DETECTOR LP digital supply 1 VP2 6 MHz CCO 9 analog supply TDA4662 sandcastle input 5 SANDCASTLE DETECTOR 2 6 13 15 n.c. n.c. n.c. n.c. DIVIDEBY-2 3 GND2 MED743 7 4, 8 i.c. 10 GND1 Product specification TDA4662 Fig.1 Block diagram. Philips Semiconductors Product specification Baseband delay line PINNING SYMBOL VP2 n.c. GND2 i.c. SAND n.c. i.c. i.c. VP1 GND1 Vo(R-Y) Vo(B-Y) n.c. Vi(B-Y) n.c. Vi(R-Y) PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 DESCRIPTION supply voltage for digital part (+5 V) not connected ground for digital part (0 V) internally connected sandcastle pulse input not connected internally connected internally connected supply voltage for analog part (+5 V) ground for analog part (0 V) ±(R-Y) output signal ±(B-Y) output signal not connec