Agilent 5991-2662EN Logic Analysis Fundamentals - Application Note c20140929 [14] free download

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Keysight Technologies Logic Analysis Fundamentals Application Note Introduction Today, a wide range of end products, such as mobile devices, radar systems, and industrial controls are found with a combination of serial and parallel bus structures. Internal FPGA signals are almost exclusively parallel bus in nature. This application note exam- ines the basics of parallel bus measurements, including functional and timing verification and debug and tracing system crashes in search of a root cause. Synchronous versus asynchronous capture in logic analyzers Before looking at specific measurement examples, it is helpful to consider the difference between synchronous and asynchronous capture and the benefits and limitations of each. Synchronous (state) capture means that the measurement system in the logic analyzer determines the logic value of digital parallel buses or control lines when there is an associated valid clock, such as a rising edge on a system clock line that is probed, as shown in Figure 1. Intermediate unsettled bus values in between valid clock edges are completely ignored by the analyzer. The bus values stored into analyzer memory represent the "states" of the bus, either state machine values or data flow. The primary purpose of such measurements is to determine if the basic functionality of the system is correct. Does the state machine move through the proper sequence of states considering the inputs to the system? For synchronous designs, this approach is often the most insight- ful, although it does require the user to specify an input clock signal to the logic analyzer. Portable logic analyzers, such as the 16850 Series, can trace buses running as fast as 1400 Mbps state data rates. Synchronous and asynchronous capture, combined with the right triggering, is the key to efficient digital system debug Threshold VInput Output (0 or 1) + Latch _ VOutput Comparator External DUT Clock Data AA OC 61 B3 Clock Clock Data 1 AA 2 OC 3 B3 Figure 1. State (Synchronous) capture 03 | Keysight | Logic Analysis Fundamentals - Application Note Synchronous versus asynchronous capture in logic analyzers (continued) In contrast, asynchronous (timing) capture means that the measurement system samples the value of a bus or individual digital lines "asynchronously" from the system under test or "not in sync" with the system, as shown in Figure 2. The measurement clock is generated by the logic analyzer rather than the target system. Portab