InterM MEQ2000 free download

File name InterM-MEQ2000 equal.pdf

www.inter-m.com MADE IN KOREA 2003.1 9017100200 SERVICE MANUAL 2 4 / 9 6 M U L T I M O D E EQUALIZER MEQ-2000 CONTENTS Electrical Adjustment Procedure 1 Micom Data 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 Specifications 15, 16, 17, 18 Electrical Parts List 19, 20, 21 Top and Bottom View of P.C. Board 22, 23, 24, 25, 26 Wiring Diagram 27 Block Diagram 28 Schematic Diagram 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54 Exploded View of Cabinet & Chassis / Mechanical Parts List 55, 56 Ass'y Drawing 57, 58 ELECTRICAL ADJUSTMENT PROCEDURE 1. ANALOG INPUT GAIN ADJUSTING 1) First, Connect Analog XLR input and Digital XLR output to test equipment (Inter-M use Audio Precision System II Cascade , It support the AES3 in/out) 2) Put the Analog Input Potentiometer (Left below in Front Panel) to Max. 3) Analog input Level of the each channel is -20dBu, And Adjust the P3 and P4 to Digital Output Level of the each channel is -20.5dBFS. When you adjust this potentiometer, Tolerance is +/- 0.1 dBFS. 2. ANALOG OUTPUT GAIN ADJUSTING 1) First, Connect Analog XLR Output and Digital XLR input to test equipment.(Inter-M use Audio Precision System II Cascade, It support the AES3 in/out) 2) Digital input Level of the each channel is -3dBFS, And Adjust the P1 and P2 to Analog Output Level of the each channel is 21dBu. 3. ANALOG OUTPUT CMRR ADJUSTING 1) First, Connect the special cable for CMRR adjusting to Analog XLR Output. The special CMRR adjusting cable is made with 300 ohm resistor that of tolerance is 0.01%.(+/- 0.03ohm) 2) Digital input Level of each channel is -3dBFS, And, Adjust the P5 and P6 to Analog Output Level is below -35dBu. 1 MICOM DATA ADSP-21065L DSP MICROCOMPUTER SUMMARY ­ High Performance Signal Computer for Communications, Audio, Automotive, Instrumentation and Industrial Applications ­ Super Harvard Architecture Computer (SHARC®) Four Independent Buses for Dual Data, Instruction, and I/O Fetch on a Single Cycle ­ 32-Bit Fixed-Point Arithmetic; 32-Bit and 40-Bit Floating-Point Arithmetic ­ 544 Kbits On-Chip SRAM Memory and Integrated I/O Peripheral ­ I2S Support, for Eight Simultaneous Receive and Transmit Channels KEY FEATURES ­ 66 MIPS, 198 MFLOPS Peak, 132 MFLOPS Sustained Perfo