SGS 4026 free download

File name 4026.pdf

HCC/HCF4026B HCC/HCF4033B DECADE COUNTERS/DIVIDERS WITH DECODED 7-SEGMENT DISPLAY OUTPUTS . . . . . . . . . . . . WITH; DISPLAY ENABLE 4026B RIPPLE BLANKING 4033B COUNTER AND 7-SEGMENT DECODING IN ONE PACKAGE EASILY INTERFACED WITH 7-SEGMENT DISPLAY TYPES FULLY STATIC COUNTER OPERATION : DC TO 6MHz (typ.) AT VDD = 10V IDEAL FOR LOW-POWER DISPLAYS DISPLAY ENABLE OUTPUT - 4026B "RIPPLE BLANKING" AND LAMP TEST - 4033B QUIESCENT CURRENT SPECIFIED TO 20V FOR HCC DEVICE STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS 5V, 10V, AND 15V PARAMETRIC RATING INPUT CURRENT OF 100nA AT 18V AND 25°C FOR HCC DEVICE 100% TESTED FOR QUIESCENT CURRENT MEETS ALL REQUIREMENTS OF JEDEC TENTATIVE STANDARD N° 13A, "STANDARD SPECIFICATIONS FOR DESCRIPTION OF "B" SERIES CMOS DEVICES" EY (Plastic Package) F (Ceramic Frit Seal Package) M1 (Micro Package) C1 (Plastic Chip Carrier) ORDER CODES : HCC40XXBF HCF40XXBM1 HCF40XXBEY HCF40XXBC1 PIN CONNECTIONS DESCRIPTION The HCC4026B/4033B (extended temperature range) and HCF4026B/4033B (intermediate temperature range) are monolithic integrated circuits, available in 16-lead dual in-line plastic or ceramic package and plastic micro package. The HCC/HCF4026B and HCC/HCF4033B each consist of a 5-stage Johnson decade counter and an output decoder which converts the Johnson code to a 7-segment decoded output for driving one stage in a numerical display. These devices are particularly advantageous in display applications where low power dissipation and/or low package count are important. Inputs common to both types are CLOCK, RESET, & CLOCK INHIBIT ; common outputs are CARRY OUT and the seven decoded outputs (a, b, c, d, e, f, g). Additional inputs and outputs for the HCC/HCF4026B include DISPLAY ENABLE input and DISPLAY ENABLE and UNGATED "CSEGMENT" outputs. Signals peculiar to the HCC/HCF4033B are RIPPLE-BLANKING INPUT AND LAMP TEST INPUT and a RIPPLE-BLANKING OUTPUT. A high RESET signal clears the deJune 1989 4026B 4033B 1/15 HCC/HCF4026B/4033B cade counter to its zero count. The counter is advanced one count at the positive clock signal transition if the CLOCK INHIBIT signal is low. Counter advancement via the clock line is inhibited when the CLOCK INHIBIT signal is high. Antilock gating is provided on the JOHNSON counter, thus assuring proper counting sequence. The CARRY-OUT (Cout) signal completes one cycle every ten CLOCK INPUT cycles and is used to clock the succeeding decade directly in a multi-decade counting chain. The seven decoded outputs (a, b, c, d, e, f, g) illuminate the proper segments in a seven segment display device used for representing the decimal numbers 0 to 9. The 7-segment outputs go high on selection in the HCC/HCF4033B ; in the HCC/HCF4026B these outputs go high only when the DISPLAY ENABLE IN is high. HCC/HCF4026B - When the DISPLAY ENABLE IN is low the seven decoded outputs are forced low regardless of the state of the counter. Activation of the display only when required results in significant