Cyrix 6x86 free download

File name M1-1.PDF

1- 6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU ® Advancing the Standards Introduction Product Overview 1. ARCHITECTURE OVERVIEW The Cyrix 6x86 CPU is a leader in the sixth generation of high performance, x86-compatible processors. Increased performance is accomplished by the use of superscalar and superpipelined design techniques. The 6x86 CPU is superscalar in that it contains two separate pipelines that allow multiple instructions to be processed at the same time. The use of advanced processing technology and the increased number of pipeline stages (superpipelining) allow the 6x86 CPU to achieve clocks rates of 100 MHz and above. Through the use of unique architectural features, the 6x86 processor eliminates many data dependencies and resource conflicts, resulting in optimal performance for both 16-bit and 32-bit x86 software. The 6x86 CPU contains two caches: a 16-KByte dual-ported unified cache and a 256-byte instruction line cache. Since the unified cache can store instructions and data in any ratio, the unified cache offers a higher hit rate than separate data and instruction caches of equal size. An increase in overall cache-to-integer unit bandwidth is achieved by supplementing the unified cache with a small, high-speed, fully associative instruction line cache. The inclusion of the instruction line cache avoids excessive conflicts between code and data accesses in the unified cache. The on-chip FPU allows floating point instructions to execute in parallel with integer instructions and features a 64-bit data interface. The FPU incorporates a four-deep instruction queue and a four-deep store queue to facilitate parallel execution. The 6x86 CPU operates from a 3.3 volt power supply resulting in reasonable power consumption at all frequencies. In addition, the 6x86 CPU incorporates a low power suspend mode, stop clock capability, and system management mode (SMM) for power sensitive applications. 1.1 Major Functional Blocks The 6x86 processor consists of five major functional blocks, as shown in the overall block diagram on the first page of this manual: · · · · · Integer Unit Cache Unit Memory Management Unit Floating Point Unit Bus Interface Unit Instructions are executed in the X and Y pipelines within the Integer Unit and also in the Floating Point Unit (FPU). The Cache Unit stores the most recently used data and instruc- PRELIMINARY 1-1 ® Integer Unit Advancing the Standards tions to allow fast access to the information by the Integer Unit and FPU. Physical addresses are calculated by the Memory Management Unit and passed to the Cache Unit and the Bus Interface Unit (BIU). The BIU provides the interface between the external system board and the processor's internal execution units. 1.2 Integer Unit The Integer Unit (Figure 1-1) provides parallel instruction execution using two seven-stage integer pipelines. Each of the two pipelines, X and Y, can process several instructions simult

File name M1-2.pdf

6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU ® Advancing the Standards Programming Interface 2. PROGRAMMING INTERFACE 2.1 Processor Initialization In this chapter, the internal operations of the 6x86 CPU are described mainly from an application programmer's point of view. Included in this chapter are descriptions of processor initialization, the register set, memory addressing, various types of interrupts and the shutdown and halt process. An overview of real, virtual 8086, and protected operating modes is also included in this chapter. The FPU operations are described separately at the end of the chapter. This manual does not--and is not intended to--describe the 6x86 microprocessor or its operations at the circuit level. The 6x86 CPU is initialized when the RESET signal is asserted. The processor is placed in real mode and the registers listed in Table 2-1 (Page 2-2) are set to their initialized values. RESET invalidates and disables the cache and turns off paging. When RESET is asserted, the 6x86 CPU terminates all local bus activity and all internal execution. During the entire time that RESET is asserted, the internal pipelines are flushed and no instruction execution or bus activity occurs. Approximately 150 to 250 external clock cycles after RESET is negated, the processor begins executing instructions at the top of physical memory (address location FFFF FFF0h). Typically, an intersegment JUMP is placed at FFFF FFF0h. This instruction will force the processor to begin execution in the lowest 1 MByte of address space. Note: The actual time depends on the clock scaling in use. Also an additional 220 clock cycles are needed if self-test is requested. PRELIMINARY 2-1 ® Processor Initialization Advancing the Standards Table 2-1. REGISTER REGISTER NAME Initialized Register Controls INITIALIZED CONTENTS COMMENTS EAX EBX ECX EDX EBP ESI EDI ESP EFLAGS EIP ES CS SS DS FS GS IDTR GDTR LDTR TR CR0 CR2 CR3 CCR (0-5) ARR (0-7) RCR (0-7) DIR0 DIR1 DR7 Accumulator Base Count Data Base Pointer Source Index Destination Index Stack Pointer Flag Word Instruction Pointer Extra Segment Code Segment Stack Segment Data Segment Extra Segment Extra Segment Interrupt Descriptor Table Register Global Descriptor Table Register Local Descriptor Table Register Task Register Machine Status Word Control Register 2 Control Register 3 Configuration Control (0-5) Address Region Registers (0-7) Region Control Registers (0-7) Device Identification 0 Device Identification 1 Debug Register 7 xxxx xxxxh xxxx xxxxh xxxx xxxxh 05 + Device ID xxxx xxxxh xxxx xxxxh xxxx xxxxh xxxx xxxxh 0000 0002h 0000 FFF0h 0000h F000h 0000h 0000h 0000h 0000h Base = 0, Limit = 3FFh xxxx xxxxh, xxxxh xxxx xxxxh, xxxxh xxxxh 6000 0010h xxxx xxxxh xxxx xxxxh 00h 00h 00h 31h or 33h (2X clock) 35h or 37h (3X clock) Step ID + Revision ID 0000 0400h 0000 0000h indicates self-test passed. Device ID = 31h or 33h (2X clock) Device ID = 35h or 37h (3X cloc

File name M1-3.pdf

6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU ® Advancing the Standards Bus Interface 3.0 6x86 BUS INTERFACE The signals used in the 6x86 CPU bus interface are described in this chapter. Figure 3-1 shows the signal directions and the major signal groupings. A description of each signal and their reference to the text are provided in Table 3-1 (Page 3-2). INTR Clock Control Reset CLK CLKMUL RESET WM_RST NMI SMI# EWBE# FLUSH# KEN# A31 - A3 PCD PWT BE7# - BE0# A20M# Interrupt Control Cache Control Address Bus WB/WT# BOFF# BREQ HOLD HLDA Address Parity Data Bus AP APCHK# D63 - D0 Bus Arbitration AHOLD Data Parity DP7 - DP0 PCHK# 6x86 CPU EADS# HIT# HITM# INV Cache Coherency CACHE# D/C# FERR# IGNNE# BHOLD FPU Error Bus Cycle Definition LOCK# M/IO# DHOLD LBA# QDUMP# SUSP# SCYC W/R# Scatter Gather Buffer ADS# ADSC# Bus Cycle Control BRDY# BRDYC# NA# SUSPA# TCK TDI TDO TMS TRST# Power Management JTAG SMIACT# 1 7 37 9 00 Figure 3-1. 6x86 CPU Functional Signal Groupings PRELIMINARY 3-1 ® Signal Description Table Advancing the Standards 3.1 Signal Description Table The Signal Summary Table (Table 3-1) describes the signals in their active state unless otherwise mentioned. Signals containing slashes (/) have logic levels defined as "1/0." For example the signal W/R#, is defined as write when W/R#=1, and as read when W/R#=0. Signals ending with a "#" character are active low. . Table 3-1. 6x86 CPU Signals Sorted by Signal Name Signal Name Description I/O Reference A20M# A20 Mask causes the CPU to mask (force to 0) the A20 address bit when driving the external address bus or performing an internal cache access. A20M# is provided to emulate the 1 MByte address wrap-around that occurs on the 8086. Snoop addressing is not effected. The Address Bus, in conjunction with the Byte Enable signals (BE7#-BE0#), provides addresses for physical memory and external I/O devices. During cache inquiry cycles, A31-A5 are used as inputs to perform cache line invalidations. Address Strobe begins a memory/I/O cycle and indicates the address bus (A31-A3, BE7#-BE0#) and bus cycle definition signals (CACHE#, D/C#, LOCK#, M/IO#, PCD, PWT, SCYC, W/R#) are valid. Cache Address Strobe performs the same function as ADS#. Address Hold allows another bus master access to the 6x86 CPU address bus for a cache inquiry cycle. In response to the assertion of AHOLD, the CPU floats AP and A31-A3 in the following clock cycle. Address Parity is the even parity output signal for address lines A31-A5 (A4 and A3 are excluded). During cache inquiry cycles, AP is the even-parity input to the CPU, and is sampled with EADS# to produce correct parity check status on the APCHK# output. Address Parity Check Status is asserted during a cache inquiry cycle if an address bus parity error has been detected. APCHK# is valid two clocks after EADS# is sampled active. APCHK# will remain asserted for one clock cycle if a parity error is dete

File name M1-4.pdf

6x86 MICROPROCESSOR Sixth-Generation Superscalar Superpipelined x86-Compatible CPU ® Advancing the Standards Electrical Specifications 4.0 4.1 ELECTRICAL SPECIFICATIONS Electrical Connections 4.1.2 Pull-Up/Pull-Down Resistors This section provides information on electrical connections, absolute maximum ratings, recommended operating conditions, DC characteristics, and AC characteristics. All voltage values in Electrical Specifications are measured with respect to VSS unless otherwise noted. 4.1.1 Power and Ground Connections and Decoupling Table 4-1 lists the input pins that are internally connected to pull-up and pull-down resistors. The pull-up resistors are connected to VCC and the pull-down resistors are connected to VSS. When unused, these inputs do not require connection to external pull-up or pull-down resistors. The SUSP# pin is unique in that it is connected to a pull-up resistor only when SUSP# is not asserted. Table 4-1. Pins Connected to Internal Pull-Up and Pull-Down Resistors SIGNAL PIN NO. RESISTOR Testing and operating the 6x86 CPU requires the use of standard high frequency techniques to reduce parasitic effects. The high clock frequencies used in the 6x86 CPU and its output buffer circuits can cause transient power surges when several output buffers switch output levels simultaneously. These effects can be minimized by filtering the DC power leads with low-inductance decoupling capacitors, using low impedance wiring, and by utilizing all of the VCC and GND pins. The 6x86 CPU contains 296 pins with 53 pins connected to VCC and 53 connected to VSS (ground). BRDYC# CLKMUL QDUMP# SMI# SUSP# TCK TDI TMS TRST# Reserved Reserved Reserved Reserved Y3 Y33 AL7 AB34 Y34 M34 N35 P34 Q33 J33 W35 Y35 AN35 20-k pull-up 20-k pull-down 20-k pull-up 20-k pull-up (see text) 20-k pull-up 20-k pull-down PRELIMINARY 4-1 ® Absolute Maximum Ratings Advancing the Standards 4.1.3 Unused Input Pins 4.2 Absolute Maximum Ratings All inputs not used by the system designer and not listed in Table 4-1 should be connected either to ground or to VCC. Connect active-high inputs to ground through a 20 k (± 10%) pull-down resistor and active-low inputs to VCC through a 20 k (± 10%) pull-up resistor to prevent possible spurious operation. 4.1.4 NC and Reserved Pins Pins designated NC have no internal connections. Pins designated RESV or RESERVED should be left disconnected. Connecting a reserved pin to a pull-up resistor, pull-down resistor, or an active signal could cause unexpected results and possible circuit malfunctions. The following table lists absolute maximum ratings for the 6x86 CPU microprocessors. Stresses beyond those listed under Table 4-2 limits may cause permanent damage to the device. These are stress ratings only and do not imply that operation under any conditions other than those listed under "Recommended Operating Conditions" Table 4-3 (Page 4-3) is possible. Exposure to conditions beyond Table 4-2 may (1) reduce device r

File name M1-5.pdf

6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU ® Advancing the Standards Mechanical Specifications 5.0 5.1 MECHANICAL SPECIFICATIONS 296-Pin SPGA Package The pin assignments for the 6x86 CPUin a 296-pin SPGA package are shown in Figure 5-1. The pins are listed by signal name in Table 5-1(Page 5-2) and by pin number in Table 5-2 (Page 5-3). Dimensions are shown in Figure 5-2 (Page 5-4) and Table 5-3 (Page 5-5). 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 AN AM AL AK AJ AH AG VSS A30 VSS A28 VSS RESV A4 A3 A29 A25 A6 A8 A7 A5 A31 A10 VSS A11 A9 VCC VSS A12 A13 VCC VSS A14 A15 VCC VSS A16 A17 VCC VSS A18 A19 VCC VSS A20 VCC VSS RESV CLK VCC VSS SCYC VCC VSS BE6# VCC VSS BE4# VCC VSS BE2# VCC FLUSH# VSS W/R# NC EADS# NC ADSC# NC AN AM AL BE0# QDUMP# HITM# HIT# D/C# PWT AP NC RESET BE7# BE5# BE3# BE1# A20M# AK BREQ ADS# HLDA AJ AH AG A22 VCC VSS VCC NC A24 A26 A27 A21 A23 LOCK# PCD VSS VCC SMIACT# VSS AF AE AD PCHK# APCHK# NC AF VCC AE AD AC AB AA Z Y X W VSS VCC VSS INTR NC SMI# NC NMI NC VSS RESV VCC VSS AC AB AA Z HOLD VCC IGNNE# WM_RST VSS NC WB/WT# RESV VSS VCC BOFF# Y X W V U T VCC VSS RESV CLKMUL NA# BRDYC# VSS VCC RESV BRDY# VCC VSS RESV SUSPA# SUSP# 6x86 CPU TOP VIEW KEN# EWBE# VSS VCC AHOLD V VCC VCC VSS VCC VSS VCC VCC INV CACHE# MI/O# VSS U T S R Q P N M L K J H G F E D C B DHOLD VSS RESV LBA# RESV VSS VCC S R Q P N M L K J H G F E D C B A BHOLD NC TRST# TMS TDI TDO TCK NC VCC D0 D60 RESV FERR# NC DP7 D62 D61 D59 VCC VSS VCC VSS VCC VSS RESV VSS D63 VSS VCC VCC VCC VSS VCC VSS D2 NC RESV D58 D56 D57 VSS VCC VCC D4 VCC D1 D5 D6 D3 DP5 D7 D42 D46 D53 D51 D49 D55 DP6 D52 VCC D54 DP0 D9 D11 D10 D8 D14 D13 D12 D17 D16 DP1 D21 D20 D19 D24 VSS D23 DP2 VSS D26 D25 D28 D27 VSS D30 D29 VSS DP3 D31 VSS D33 D32 VSS D35 D34 VSS D37 D36 VSS D39 D38 VSS D40 DP4 VSS D44 D45 VSS D48 D47 D43 D50 NC NC VSS VCC VCC A NC D15 D18 D22 VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC D41 NC 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 1740200 Figure 5-1. 296-Pin SPGA Package Pin Assignments PRELIMINARY 5-1 ® 296-Pin SPGA Package Advancing the Standards Table 5-1. 296-Pin SPGA Package Signal Names Sorted by Pin Number Pin A3 A5 A7 A9 A11 A13 A15 A17 A19 A21 A23 A25 A27 A29 A31 A33 A35 A37 B2 B4 B6 B8 B10 B12 B14 B16 B18 B20 B22 B24 B26 B28 B30 B32 B34 B36 C1 C3 C5 C7 C9 C11 C13 C15 C17 C19 C21 C23 C25 C27 Signal NC D41 Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc Vcc D22 D18 D15 NC NC D43 Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss D20 D16 D13 D11 NC D47 D45 DP4 D38 D36 D34 D32 D31 D29 D27 D25 DP2 D24 Pin C29 C31 C33 C35 C37 D2 D4 D6 D8 D10 D12 D14 D16 D18 D20 D22 D24 D26 D28 D30 D32 D34 D36 E1 E3 E5 E7 E9 E33 E35 E37 F2 F4 F6 F34 F36 G1 G3 G5 G33 G35 G37 H2 H4 H34

File name M1-6.pdf

6x86 PROCESSOR Superscalar, Superpipelined, Sixth-generation, x86 Compatible CPU ® Advancing the Standards Instruction Set 6. INSTRUCTION SET 6.1 Instruction Set Summary This section summarizes the 6x86 CPU instruction set and provides detailed information on the instruction encodings. All instructions are listed in the CPU Instruction Set Summary Table (Table 6-20, Page 6-14), and the FPU Instruction Set Summary Table (Table 6-22, Page 6-30). These tables provide information on the instruction encoding, and the instruction clock counts for each instruction. The clock count values for both tables are based on the assumptions described in Section 6.3. Depending on the instruction, the 6x86 CPU instructions follow the general instruction format shown in Figure 6-1. These instructions vary in length and can start at any byte address. An instruction consists of one or more bytes that can include: prefix byte(s), at least one opcode byte(s), mod r/m byte, s-i-b byte, address displacement byte(s) and immediate data byte(s). An instruction can be as short as one byte and as long as 15 bytes. If there are more than 15 bytes in the instruction a general protection fault (error code of 0) is generated. P P P P P P P P T T T T T T T T mod 0 76 7 0 7 optional prefix byte(s) op-code (one or two bytes) R R R r/m ss 543 210 76 mod r/m byte index 543 s-i-b byte base 21 0 32 16 8 none 32 16 8 none P = prefix bit T = opcode bit R = opcode bit or reg bit address displacement (4, 2, 1 bytes, or none) immediate data (4, 2, 1 bytes, or none) 1703103 register and address mode specifier Figure 6-1. Instruction Set Format PRELIMINARY 6-1 ® Instruction Set Summary Advancing the Standards 6.2 General Instruction Fields The fields in the general instruction format at the byte level are listed in Table 6-1. Table 6-1. Instruction Fields FIELD NAME DESCRIPTION WIDTH Optional Prefix Byte(s) Specifies segment register override, address and operand size, repeat elements in string instruction, LOCK# assertion. Opcode Byte(s) Identifies instruction operation. mod and r/m Byte Address mode specifier. s-i-b Byte Scale factor, Index and Base fields. Address Displacement Address displacement operand. Immediate data Immediate data operand. 1 or more bytes 1 or 2 bytes 1 byte 1 byte 1, 2 or 4 bytes 1, 2 or 4 bytes 6.2.1 Optional Prefix Bytes Prefix bytes can be placed in front of any instruction. The prefix modifies the operation of the next instruction only. When more than one prefix is used, the order is not important. There are five type of prefixes as follows: 1. 2. 3. 4. 5. Segment Override explicitly specifies which segment register an instruction will use for effective address calculation. Address Size switches between 16- and 32-bit addressing. Selects the inverse of the default. Operand Size switches between 16- and 32-bit operand size. Selects the inverse of the default. Repeat is used with a string instruction which causes the instruction t