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MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14506UB Dual 2-Wide, 2-Input Expandable AND-OR-INVERT Gate The MC14506UB is an expandable AND­OR­INVERT gate with inhibit and 3­state output. The expand option allows cascading with any other gate, which may be carried as far as desired as long as the propagation delay added with each gate is considered. For example, the second AOI gate in this device may be used to expand the first gate, giving an expanded 4­wide, 2­input AOI gate. This device is useful in data control and digital multiplexing applications. · · · · · 3­State Output Separate Inhibit Line Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low­Power TTL Loads or One Low­Power Schottky TTL Load Over the Rated Temperature Range L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXUBCP MC14XXXUBCL MC14XXXUBD Plastic Ceramic SOIC ООООООООООООООООООООО ООООООООООООООООООООО ООООООООООООООООООООО ООООООООООООООООООООО MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD Parameter DC Supply Voltage Value Unit V V mA mW ­ 0.5 to + 18.0 Vin, Vout Iin, Iout PD Tstg TL Input or Output Voltage (DC or Transient) Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature Lead Temperature (8­Second Soldering) ­ 0.5 to VDD + 0.5 ± 10 500 ­ 65 to + 150 260 TA = ­ 55° to 125°C for all packages. _C _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: ­ 12 mW/_C From 100_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS (Vin or Vout) VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. v v TRUTH TABLE A B C D E Inhibit Disable 0 0 0 0 0 X X X 1 X 0 0 0 0 0 0 0 0 0 1 Z 1 1 1 1 1 0 0 0 0 High Impedance 0 0 0 X 0 X X 0 0 1 X X 0 0 X 0 X X 1 X 0 X 0 X 0 X 1 X 1 1 1 1 1 X X 0 LOGIC DIAGRAM AA BA CA DA EA 1 2 3 4 5 15 ZA INH 6 DIS 14 EB 13 DB 12 CB 11 BB 10 AB 9 3­STATE OUTPUT DISABLE VDD = PIN 16 VSS = PIN 8 X 1 X X X X X X X X X X X X X = Don't Care 7 ZB Z = (AB + CD + E + I) REV 3 1/94 ©MOTOROLA CMOS LOGIC DATA Motorola, Inc. 1995 MC14506UB 1 ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООООООООООООООО ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 ­ 3.0 ­ 0.64 ­ 1.6 ­ 4.2 0.6