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MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14508B Dual 4-Bit Latch The MC14508B dual 4­bit latch is constructed with MOS P­channel and N­channel enhancement mode devices in a single monolithic structure. The part consists of two identical, independent 4­bit latches with separate Strobe (ST) and Master Reset (MR) controls. Separate Disable inputs force the outputs to a high impedance state and allow the devices to be used in time sharing bus line applications. These complementary MOS latches find primary use in buffer storage, holding register, or general digital logic functions where low power dissipation and/or high noise immunity is desired. · 3­State Output · Supply Voltage Range = 3.0 Vdc to 18 Vdc · Capable­of Driving Two Low­power TTL Loads or One Low­power Schottky TTL Load over the Rated Temperature Range MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol Parameter VDD Vin, Vout Iin, Iout PD Tstg DC Supply Voltage Value L SUFFIX CERAMIC CASE 623 P SUFFIX PLASTIC CASE 709 DW SUFFIX SOIC CASE 751E ООООООООООООООООООООО ООООООООООООООООООООО ООООООООООООООООООООО Unit V V ­ 0.5 to + 18.0 ± 10 500 ­ 65 to + 150 Input or Output Voltage (DC or Transient) ­ 0.5 to VDD + 0.5 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Temperature mA mW ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBDW Plastic Ceramic SOIC TA = ­ 55° to 125°C for all packages. _C 1 2 3 4 6 8 10 BLOCK DIAGRAM MR ST DIS D0 D1 D2 D3 Q0 Q1 Q2 Q3 5 7 9 11 TL Lead Temperature (8­Second Soldering) 260 _C * Maximum Ratings are those values beyond which damage to the device may occur. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C Ceramic "L" Packages: ­ 12 mW/_C From 100_C To 125_C TRUTH TABLE MR 0 0 0 0 0 0 1 X ST 1 1 1 1 1 0 X X Disable 0 0 0 0 0 0 0 1 D3 0 0 0 0 1 X X X D2 0 0 0 1 0 X X X D1 0 0 1 0 0 X X X D0 0 1 0 0 0 X X X 0 Q3 0 0 0 0 1 Q2 0 0 0 1 0 Q1 0 0 1 0 0 Q0 0 1 0 0 0 Latched 0 0 0 High Impedance 13 14 15 16 18 20 22 MR ST DIS D0 D1 D2 D3 Q0 Q1 Q2 Q3 17 19 21 23 X = Don't Care CIRCUIT DIAGRAM DIS MR ST VDD = PIN 24 VSS = PIN 12 VDD Dn Qn (TO OTHER THREE LATCHES) VSS REV 3 1/94 ©MC14508B 1995 Motorola, Inc. 344 MOTOROLA CMOS LOGIC DATA ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООООООООООООООО ОООООООООООООООООООООООООООООООООО ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0 10 15 15 -- 5.0 10 15 5.0 10 15 ­ 3.0 ­ 0.64 ­ 1.6 ­ 4.2 0.64 1.6 4.2 -- -- -- -- -- -- -- -- -- -- -- -- ± 0.1 -- 5.0 10 20 ­ 2.4 ­ 0.51 ­ 1.3 ­ 3.4 0.51 1.3 3.4 -- -- -- -- -- ­ 4.2 ­ 0.88 ­ 2.25 ­ 8.8 0.88 2.25 8.8 ± 0.00001 5.0 0.005 0.010 0.015 -- -- -- -- -- -- -- ± 0.1 7.5 5.0 10 20 ­ 1.7 ­ 0.36 ­ 0.9 ­ 2.4 0.36 0.9 2.4 -- -- -- -- -- -- -- -- -- -- -- -- ± 1.0 -- 150 300 600 mAdc 3.5 7.0 11 -- -- -- 3.5 7.0 11 2.75 5.50 8.25 -