Philips 4738 free download

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: · The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC · The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4738V LSI IEC/IEEE bus interface Product specification File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product specification IEC/IEEE bus interface DESCRIPTION The HEF4738V is an implementation of the IEC-bus as described in IEC report 66 CO 22 (interface system for programmable measuring apparatus) as well as in IEEE standard 488-1975 (standard digital interface for programmable instrumentation). Together with bus-drivers, level converters and multiplexers it is suitable for connecting electronic programmable and non-programmable equipment to an IEC/IEEE interface bus. All inputs have standard HE4000B family levels. In the circuit the following standard interface functions are incorporated: HEF4738V LSI · Complete source handshake (subset SH1) · Complete acceptor handshake (subset AH1) · Basic talker with serial poll and talk-only mode (when It = LOW, subset T1; It = HIGH, subset T5) · Basic listener with listen-only mode (when It = LOW, subset L1; It = HIGH, subset L3) · Complete service request (subset SR1) · Complete remote local (subset RL1) · Remote parallel poll configuration (subset PP1) · Complete device clear (subset DC1) · Complete device trigger (subset DT1) · Some controller facilities Fig.1 Basic IEC/IEEE bus interface using the HEF4738V. SUPPLY VOLTAGE RATING -0,5 to 18 RECOMMENDED OPERATING 4,5 to 12,5 V FAMILY DATA, IDD LIMITS category LSI See Family Specifications January 1995 2 Philips Semiconductors Product specification IEC/IEEE bus interface GENERAL DESCRIPTION The inputs IRFD, IDAC, IDAV, IIFC, IREN, IATN, IIDY and IDIO1 to IDIO7 must be connected via an inverting TTL to LOCMOS level converter to the respective bus lines: NRFD, NDAC, DAV, IFC, REN, ATN, IDY and DIO1 to DIO7. The outputs ORFD, ODAC, ODAV and OSRQ can drive one standard TTL load and are suitable for driving NRFD, NDAC, DAV and SRQ via an inverting bus-driver circuit. The parallel poll outputs OP1, OP2, OP3 and OPP can also drive one standard TTL load. Outputs OP1, OP2 and OP3 are connected to flip-flops, which store the attendant bits P1, P2 and P3 of the last PPE message. OP1, OP2 and OP3 have to be decoded externally and multiplexed to the DIO-lines when OPP is LOW. All other output stages are standard HE4000B family. Most of the functions in the IEC/IEEE interface IC are realized with synchronous sequential logic, which is driven from the clock input CP. HIGH to LOW transitions are used to synchronize input signals and LOW to HIGH transitions trigger the internal flip-flops. In order to meet the IEC/IEEE timing specifications, the maximum clock frequency is 2 MHz. The maximum data transfer is then 200 kbytes/second. Input Irdy (not ready for next message) and output Odvd (data valid device) are intended fo