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Electronic circuits, electronic components datasheets and schematics| File information: | |
| File name: | 4035.pdf |
| Size: | 224 kB |
| Extension: | |
| Mfg: | Motorola |
| Model: | 4035 🔎 |
| Original: | CMOS 4xxx 🔎 |
| Descr: | 4-bit parallel In-Out shift register |
| Group: | Electronics > Components > Integrated circuits |
| Uploaded: | 21-04-2005 |
| User: | dupator |
| Multipart: | No multipart |
| Information about the files in archive: | ||
| Decompress result: | OK | |
| Extracted files: | 1 | |
File name 4035.pdf MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC14035B 4-Bit Parallel-In/Parallel-Out Shift Register The MC14035B 4bit shift register is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. It consists of a 4stage clocked serialshift register with synchronous parallel inputs and buffered parallel outputs. The Parallel/Serial (P/S) input allows serialright shifting of data or synchronous parallel loading via inputs DP0 thru DP3. The True/Complement (T/C) input determines whether the outputs display the Q or Q outputs of the flipflop stages. JK logic forms the serial input to the first stage. With the J and K inputs connected together they operate as a serial "D" input. This device may be effectively used for shiftright/shiftleft registers, paralleltoserial/serialtoparallel conversion, sequence generation, up/ down Johnson or ring counters, pseudorandom code generation, frequency and phase comparators, sample and hold registers, etc . . . · · · · · · · · · · · 4Stage Clocked SerialShift Operation Synchronous Parallel Loading of all Four Stages JK Serial Inputs on First Stage Asynchronous True/Complement Control of all Outputs Fully Static Operation Asynchronous Master Reset Data Transfer Occurs on the PositiveGoing Clock Transition No Limit on Clock Rise and Fall Times All Inputs are Buffered Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Lowpower TTL Loads or One Lowpower Schottky TTL Load Over the Rated Temperature Range Parameter Value L SUFFIX CERAMIC CASE 620 P SUFFIX PLASTIC CASE 648 D SUFFIX SOIC CASE 751B ORDERING INFORMATION MC14XXXBCP MC14XXXBCL MC14XXXBD Plastic Ceramic SOIC TA = 55° to 125°C for all packages. PIN ASSIGNMENT Q0 T/C K J R C P/S VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q1 Q2 Q3 DP3 DP2 DP1 DP0 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎ Î Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ Î Î ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ MAXIMUM RATINGS* (Voltages Referenced to VSS) Symbol VDD DC Supply Voltage Unit V V 0.5 to + 18.0 Vin, Vout lin, lout PD Input or Output Voltage (DC or Transient) 0.5 to VDD + 0.5 ± 10 500 Input or Output Current (DC or Transient), per Pin Power Dissipation, per Package Storage Tem | ||
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