File name 4106.pdfMC14106B Hex Schmitt Trigger
The MC14106B hex Schmitt Trigger is constructed with MOS Pchannel and Nchannel enhancement mode devices in a single monolithic structure. These devices find primary use where low power dissipation and/or high noise immunity is desired. The MC14106B may be used in place of the MC14069UB hex inverter for enhanced noise immunity or to "square up" slowly changing waveforms.
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14 PDIP14 P SUFFIX CASE 646 1 14 SOIC14 D SUFFIX CASE 751A 14106B AWLYWW 1 14 TSSOP14 DT SUFFIX CASE 948G 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week 14 106B ALYW MC14106BCP AWLYYWW
· Increased Hysteresis Voltage Over the MC14584B · Supply Voltage Range = 3.0 Vdc to 18 Vdc · Capable of Driving Two Lowpower TTL Loads or One Lowpower · PinforPin Replacement for CD40106B and MM74C14 · Can Be Used to Replace the MC14584B or MC14069UB
Schottky TTL Load Over the Rated Temperature Range
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.)
Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8Second Soldering) Value 0.5 to +18.0 0.5 to VDD + 0.5 ±10 500 55 to +125 65 to +150 260 Unit V V mA mW °C °C °C
ORDERING INFORMATION
Device MC14106BCP MC14106BD MC14106BDR2 MC14106BDT MC14106BDTR2 Package PDIP14 SOIC14 SOIC14 TSSOP14 Shipping 2000/Box 55/Rail 2500/Tape & Reel 96/Rail
1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open.
TSSOP14 2500/Tape & Reel
© Semiconductor Components Industries, LLC, 2000
1
August, 2000 Rev. 4
Publication Order Number: MC14106B/D
MC14106B
LOGIC DIAGRAM
1 3 5 9 11 13 VDD = PIN 14 VSS = PIN 7 2 4 6 8 10 12
EQUIVALENT CIRCUIT SCHEMATIC (1/6 OF CIRCUIT SHOWN)
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