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MC14562B 128-Bit Static Shift Register The MC14562B is a 128­bit static shift register constructed with MOS P­channel and N­channel enhancement mode devices in a single monolithic structure. Data is clocked in and out of the shift register on the positive edge of the clock input. Data outputs are available every 16 bits, from 16 through bit 128. This complementary MOS shift register is primarily used where low power dissipation and/or high noise immunity is desired. http://onsemi.com · · · · · Diode Protection on All Inputs Fully Static Operation Cascadable to Provide Longer Shift Register Lengths Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low­power TTL Loads or One Low­power Schottky TTL Load Over the Rated Temperature Range A WL, L YY, Y WW, W MARKING DIAGRAMS 14 PDIP­14 P SUFFIX CASE 646 MC14562BCP AWLYYWW 1 = Assembly Location = Wafer Lot = Year = Work Week MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to +18.0 ­0.5 to VDD + 0.5 ±10 500 ­55 to +125 ­65 to +150 260 Unit V V mA mW °C °C °C ORDERING INFORMATION Device MC14562BCP Package PDIP­14 Shipping 25/Rail 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2000 1 August, 2000 ­ Rev. 4 Publication Order Number: MC14562B/D MC14562B PIN ASSIGNMENT Q64 Q96 Q128 NC CLOCK Q112 VSS 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VDD Q32 DATA NC Q16 Q48 Q80 NC = NO CONNECTION BLOCK DIAGRAM Q16 Q32 Q48 Q64 Q80 Q96 Q112 Q128 10 13 9 1 8 2 6 3 12 DATA 5 CLOCK Pins 4 and 11 not used. VDD = PIN 14 VSS = PIN 7 LOGIC DIAGRAM CLOCK 5 DATA IN 12 D Q C 1 D Q C 2 D Q C 3 D Q C 16 D Q C 17 D Q C 32 D Q C 33 D Q C 48 D Q C 49 D Q C 64 10 Q16 D Q C 65 D Q C 80 D Q C 81 D Q C 96 D Q C 97 D Q C 112 D Q C 113 D Q C 128 13 Q32 9 Q48 1 Q64 8 Q80 2 Q96 6 Q112 3 Q128 http://onsemi.com 2 MC14562B ООООООООООООООООООООООООООООООООО ООООООООООООООООООООООООООООООООО ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) Characteristic Symbol VOL VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source 5.0 5.0 10 15 IOL 5.0