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MC14174B Hex Type D Flip-Flop The MC14174B hex type D flip­flop is constructed with MOS P­channel and N­channel enhancement mode devices in a single monolithic structure. Data on the D inputs which meets the setup time requirements is transferred to the Q outputs on the positive edge of the clock pulse. All six flip­flops share common clock and reset inputs. The reset is active low, and independent of the clock. http://onsemi.com MARKING DIAGRAMS 16 PDIP­16 P SUFFIX CASE 648 MC14174BCP AWLYYWW 1 16 SOIC­16 D SUFFIX CASE 751B 14174B AWLYWW 1 · · · · · · Static Operation All Inputs and Outputs Buffered Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Capable of Driving Two Low­Power TTL Loads or One Low­Power Schottky TTL Load over the Rated Temperature Range Functional Equivalent to TTL 74174 MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to +18.0 ­0.5 to VDD + 0.5 ±10 500 ­55 to +125 ­65 to +150 260 Unit V V mA mW °C °C °C A WL, L YY, Y WW, W SOEIAJ­16 F SUFFIX CASE 966 16 MC14174B ALYW 1 = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION Device MC14174BCP MC14174BD MC14174BDR2 MC14174BF MC14174BFEL Package PDIP­16 SOIC­16 SOIC­16 SOEIAJ­16 SOEIAJ­16 Shipping 2000/Box 48/Rail 2500/Tape & Reel See Note 1. See Note 1. 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. © Semiconductor Components Industries, LLC, 2000 1 August, 2000 ­ Rev. 4 Publication Order Number: MC14174B/D MC14174B PIN ASSIGNMENT R Q0 D0 D1 Q1 D2 Q2 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q5 D5 D4 Q4 D3 Q3 C BLOCK DIAGRAM 9 1 3 4 6 11 13 14 CLOCK RESET D0 D1 D2 D3 D4 D5 Q0 Q1 Q2 Q3 Q4 Q5 2 5 7 10 12 15 VDD = PIN 16 VSS = PIN 8 TRUTH TABLE (Positive Logic) Inputs Clock Data 0 1 X X Reset 1 1 1 0 Output Q 0 1 Q 0 X X = Don't Care No Change http://onsemi.com 2 ООО О О О О О ООООООООООООООООООООООООООООООО О О О О О О О О О ОООООООООООООООООООООООООООООООО ООООООООООООООООООООО