ON SEMICONDUCTOR 4526 free download

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MC14526B Presettable 4-Bit Down Counters The MC14526B binary counter is constructed with MOS P­channel and N­channel enhancement mode devices in a monolithic structure. This device is presettable, cascadable, synchronous down counter with a decoded "0" state output for divide­by­N applications. In single stage applications the "0" output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide­by­N operation with no additional gates required. The Inhibit input allows disabling of the pulse counting function. Inhibit may also be used as a negative edge clock. This complementary MOS counter can be used in frequency synthesizers, phase­locked loops, and other frequency division applications requiring low power dissipation and/or high noise immunity. http://onsemi.com MARKING DIAGRAMS 16 PDIP­16 P SUFFIX CASE 648 MC14526BCP AWLYYWW 1 16 SOIC­16 DW SUFFIX CASE 751G 1 16 SOEIAJ­16 F SUFFIX CASE 966 MC14526B ALYW 1 Unit V V mA mW °C °C °C A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week 14526B · Supply Voltage Range = 3.0 Vdc to 18 Vdc · Logic Edge­Clocked Design -- Incremented on Positive Transition · Asynchronous Preset Enable · Capable of Driving Two Low­power TTL Loads or One Low­power Schottky TTL Load Over the Rated Temperature Range of Clock or Negative Transition of Inhibit AWLYYWW MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Operating Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to +18.0 ­0.5 to VDD + 0.5 ±10 500 ­55 to +125 ­65 to +150 260 ORDERING INFORMATION Device MC14526BCP MC14526BDW MC14526BDWR2 MC14526BF Package PDIP­16 SOIC­16 SOIC­16 SOEIAJ­16 Shipping 2000/Box 47/Rail 1000/Tape & Reel See Note 1. 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. © Semiconductor Components Industries, LLC, 2000 1 August, 2000 ­ Rev. 4 Publication Order Number: MC14526B/D MC14526B PIN ASSIGNMENT Q3 P3 PE INHIBIT P0 CLOCK VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q2 P2 CF 0" P1 RESET Q1 FUNCTION TA