ON SEMICONDUCTOR 4175 free download

File name 4175.pdf

MC14175B Quad Type D Flip-Flop The MC14175B quad type D flip­flop is constructed with MOS P­channel and N­channel enhancement mode devices in a single monolithic structure. Each of the four flip­flops is positive­edge triggered by a common clock input (C). An active­low reset input (R) asynchronously resets all flip­flops. Each flip­flop has independent Data (D) inputs and complementary outputs (Q and Q). These devices may be used as shift register elements or as type T flip­flops for counter and toggle applications. http://onsemi.com MARKING DIAGRAMS 16 PDIP­16 P SUFFIX CASE 648 MC14175BCP AWLYYWW 1 16 SOIC­16 D SUFFIX CASE 751B 1 16 14175B AWLYWW · · · · · · · Complementary Outputs Static Operation All Inputs and Outputs Buffered Diode Protection on All Inputs Supply Voltage Range = 3.0 Vdc to 18 Vdc Output Compatible with Two Low­Power TTL Loads or One Low­Power Schottky TTL Load Functional Equivalent to TTL 74175 MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.) Symbol VDD Vin, Vout Iin, Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input or Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 3.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to +18.0 ­0.5 to VDD + 0.5 ±10 500 ­55 to +125 ­65 to +150 260 Unit V V mA mW A WL, L YY, Y WW, W SOEIAJ­16 F SUFFIX CASE 966 1 MC14175B ALYW = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION °C °C °C Device MC14175BCP MC14175BD MC14175BDR2 MC14175BF MC14175BFEL Package PDIP­16 SOIC­16 SOIC­16 SOEIAJ­16 SOEIAJ­16 Shipping 2000/Box 48/Rail 2500/Tape & Reel See Note 1. See Note 1. 2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. 1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative. © Semiconductor Components Industries, LLC, 2000 1 August, 2000 ­ Rev. 4 Publication Order Number: MC14175B/D MC14175B PIN ASSIGNMENT R Q0 Q0 D0 D1 Q1 Q1 VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD Q3 Q3 D3 D2 Q2 Q2 C BLOCK DIAGRAM 9 1 4 5 12 13 CLOCK RESET D0 D1 D2 D3 Q0 Q0 Q1 Q1 Q2 Q2 Q3 Q3 2 3 7 6 10 11 15 14 VDD = PIN 16 VSS = PIN 8 TRUTH TABLE Inputs Clock Data 0 1 X X Reset 1 1 1 0 Q 0 1 Q 0 Outputs Q 1 0 Q 1 X X = Don't Care No Change http://onsemi.com 2 ООО О О О О О ОООООО