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CD4504BMS December 1992 CMOS Hex Voltage Level Shifter for TTL-to-CMOS or CMOS-to-CMOS Operation Pinout CD4504BMS TOP VIEW Features · High Voltage Type (20V Rating) · Independence of Power Supply Sequence Considerations - VCC can Exceed VDD - Input Signals can Exceed Both VCC and VDD · Up and Down Level Shifting Capability · Shiftable Input Threshold for Either CMOS or TTL Compatibility · 100% Tested for Quiescent Current at 20V · 5V, 10V and 15V Parametric Ratings · Standardized Symmetrical Output Characteristics · Maximum Input Current of 1µA at 18V Over Full Package Temperature Range; 100nA at 18V and +25oC · Meets All Requirements of JEDEC Tentative Standard No. 13B, "Standard Specifications for Description of `B' Series CMOS Devices" VCC 1 16 VDD 15 FOUT 14 FIN 13 SELECT 12 EOUT 11 EIN 10 DOUT 9 DIN AOUT 2 AIN BOUT BIN COUT CIN VSS 3 4 5 6 7 8 Functional Diagram VCC VDD LEVEL SHIFTER OUT (2, 4, 6, 10, 12, 15) Description CD4504BMS hex voltage level shifter consists of six circuits which shift input signals from the VCC logic level to the VDD logic level. To shift TTL signals to CMOS logic levels, the SELECT input is at the VCC HIGH logic state. When the SELECT input is at a LOW logic state, each circuit translates signals from one CMOS level to another. The CD4504BMS is supplied in these 16-lead outline packages: Frit Seal DIP Ceramic Flatpack H1F H6W * IN (3, 5, 7, 9, 11, 14) SELECT * 13 TTL/CMOS MODE SELECT VCC = PIN 1 VDD = PIN 16 VSS = PIN 8 VDD * ALL INPUTS ARE PROTECTED BY CMOS PROTECTION NETWORK VSS CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999 File Number 3336 7-1140 Specifications CD4504BMS Absolute Maximum Ratings DC Supply Voltage Range, (VDD) . . . . . . . . . . . . . . . -0.5V to +20V (Voltage Referenced to VSS Terminals) Input Voltage Range, All Inputs . . . . . . . . . . . . .-0.5V to VDD +0.5V DC Input Current, Any One Input . . . . . . . . . . . . . . . . . . . . . . . .±10mA Operating Temperature Range . . . . . . . . . . . . . . . . -55oC to +125oC Package Types D, F, K, H Storage Temperature Range (TSTG) . . . . . . . . . . . -65oC to +150oC Lead Temperature (During Soldering) . . . . . . . . . . . . . . . . . +265oC At Distance 1/16 ± 1/32 Inch (1.59mm ± 0.79mm) from case for 10s Maximum Reliability Information Thermal Resistance . . . . . . . . . . . . . . . . ja jc Ceramic DIP and FRIT Package . . . . . 80oC/W 20oC/W Flatpack Package . . . . . . . . . . . . . . . . 70oC/W 20oC/W o Maximum Package Power Dissipation (PD) at +125 C For TA = -55oC to +100oC (Package Type D, F, K) . . . . . . 500mW For TA = +100oC to +125oC (Package Type D, F, K) . . . . . Derate Linearity at 12mW/oC to 200mW Device Dissipation per Output Transistor . . . . . . . . . . . . . . . 100mW For TA = Full Package Temperature Range (All Package Types) Junction Temperature . . . . . . . . . . . . . . .