File name 4551.pdfMC14551B Quad 2-Channel Analog Multiplexer/Demultiplexer
The MC14551B is a digitallycontrolled analog switch. This device implements a 4PDT solid state switch with low ON impedance and very low OFF Leakage current. Control of analog signals up to the complete supply voltage range can be achieved.
http://onsemi.com MARKING DIAGRAMS
16 PDIP16 P SUFFIX CASE 648 MC14551BCP AWLYYWW 1 16 SOIC16 D SUFFIX CASE 751B 1 14551B AWLYWW
· Triple Diode Protection on All Control Inputs · Supply Voltage Range = 3.0 Vdc to 18 Vdc · Analog Voltage Range (VDD VEE) = 3.0 to 18 V · · · ·
Note: VEE must be v VSS Linearized Transfer Characteristics Low Noise -- 12 nVCycle, f 1.0 kHz typical For Low RON, Use The HC4051, HC4052, or HC4053 HighSpeed CMOS Devices Switch Function is Break Before Make
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MAXIMUM RATINGS (2.)
Symbol VDD Parameter Value Unit V V DC Supply Voltage Range (Referenced to VEE, VSS VEE) 0.5 to + 18.0 Vin, Vout Input or Output Voltage (DC or Transient) (Referenced to VSS for Control Input & VEE for Switch I/O) Input Current (DC or Transient), per Control Pin Switch Through Current Power Dissipation, per Package Ambient Temperature Range Storage Temperature Range Lead Temperature (8Second Soldering)
(3.)
16 SOEIAJ16 F SUFFIX CASE 966 1 A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week MC14551B ALYW
0.5 to VDD + 0.5
Iin Isw PD TA Tstg TL
± 10 ± 25 500 55 to + 125 65 to + 150 260
mA mA mW _C _C _C
ORDERING INFORMATION
Device MC14551BCP MC14551BD MC14551BDR2 MC14551BF Package PDIP16 SOIC16 SOIC16 SOEIAJ16 Shipping 2000/Box 48/Rail 2500/Tape & Reel See Note 1.
2. Maximum Ratings are those values beyond which damage to the device may occur. 3. Temperature Derating: Plastic "P and D/DW" Packages: 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this highimpedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD for control inputs and VEE (Vin or Vout) VDD for Switch I/O. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS, VEE or VDD). Unused outputs must be left open.
1. For ordering information on the EIAJ version of the SOIC packages, please contact your local ON Semiconductor representative.
© Semiconductor Components Industries, LLC, 2000
1
August, 2000 Rev. 4
Publication Order Number: MC14551B/D
MC14551B
PIN ASSIGNMENT
W1 X0 X1 X Y Y0 VEE VSS 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VDD W0 W Z Z1 Z0 Y1 CONTROL
9 15 1 2 3 6 10 11 12
CONTROL W W0 W1 X0 X1 Y0 Y1 Z0 Z1 X
14 4 COMMONS OUT/IN
SWITCHES IN/OUT
Y Z
5 13
VDD = Pin 16 VSS = Pin 8 VEE = Pin 7
Control 0 1
ON W0 X0 Y0 Z0 W1 X1 Y1 Z1
NOTE: Control Input referenced to VSS, Analog Inputs and Outputs r |