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MC14553B 3-Digit BCD Counter The MC14553B 3­digit BCD counter consists of 3 negative edge triggered BCD counters that are cascaded synchronously. A quad latch at the output of each counter permits storage of any given count. The information is then time division multiplexed, providing one BCD number or digit at a time. Digit select outputs provide display control. All outputs are TTL compatible. An on­chip oscillator provides the low­frequency scanning clock which drives the multiplexer output selector. This device is used in instrumentation counters, clock displays, digital panel meters, and as a building block for general logic applications. http://onsemi.com MARKING DIAGRAMS 16 PDIP­16 P SUFFIX CASE 648 MC14553BCP AWLYYWW 1 · · · · · · · TTL Compatible Outputs On­Chip Oscillator Cascadable Clock Disable Input Pulse Shaping Permits Very Slow Rise Times on Input Clock Output Latches Master Reset 16 SOIC­16 DW SUFFIX CASE 751G 1 14553B AWLYYWW MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 1.) Symbol VDD Vin, Vout Iin Iout PD TA Tstg TL Parameter DC Supply Voltage Range Input or Output Voltage Range (DC or Transient) Input Current (DC or Transient) per Pin Output Current (DC or Transient) per Pin Power Dissipation, per Package (Note 2.) Ambient Temperature Range Storage Temperature Range Lead Temperature (8­Second Soldering) Value ­0.5 to +18.0 ­0.5 to VDD + 0.5 ±10 +20 500 ­55 to +125 ­65 to +150 260 Unit V V mA A WL, L YY, Y WW, W = Assembly Location = Wafer Lot = Year = Work Week ORDERING INFORMATION mA Device mW °C °C °C MC14553BCP MC14553BDW Package PDIP­16 SOIC­16 Shipping 25/Rail 47/Rail 1. Maximum Ratings are those values beyond which damage to the device may occur. 2. Temperature Derating: Plastic "P and D/DW" Packages: ­ 7.0 mW/_C From 65_C To 125_C This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high­impedance circuit. For proper operation, Vin and Vout should be constrained to the range VSS v (Vin or Vout) v VDD. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either VSS or VDD). Unused outputs must be left open. © Semiconductor Components Industries, LLC, 2001 1 February, 2001 ­ Rev. 5 Publication Order Number: MC14553B/D MC14553B 4 CIA 12 10 11 13 CLOCK LE DIS MR 3 CIB Q0 Q1 Q2 Q3 O.F. DS1 DS2 DS3 VDD = PIN 16 VSS = PIN 8 9 7 6 5 14 2 1 15 Figure 1. Block Diagram TRUTH TABLE Inputs Master Reset 0 0 0 0 0 0 0 0 1 X = Don't Care Clock Disable 0 0 1 LE 0 0 X 0 0 X 1 0 Outputs No Change Advance No Change Advance No Change No Change Latched Latched Q0 = Q1 = Q2 = Q3 = 0 X 1 1 0 X X X X X X X http://onsemi.com 2 MC14553B ООООООООООООООООООООООООООООООООО ООООООООООООООООООООООООООООООООО ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS) VDD Vdc 5.0 10 15 5.0 10 15 5.0 10 15 VIH 5.0 10 15 IOH Source -